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Patent # Description
2018/0174999 DIE SIDEWALL INTERCONNECTS FOR 3D CHIP ASSEMBLIES
A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are...
2018/0174998 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Method for manufacturing a semiconductor device includes: preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the...
2018/0174997 BONDING MACHINES FOR BONDING SEMICONDUCTOR ELEMENTS, METHODS OF OPERATING BONDING MACHINES, AND TECHNIQUES FOR...
A method of operating a bonding machine is provided. The method includes the steps of: (a) carrying a semiconductor element with a transfer tool; and (b)...
2018/0174996 WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE
A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the...
2018/0174995 BONDED STRUCTURES
A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature....
2018/0174994 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant...
2018/0174993 UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED...
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one...
2018/0174992 SEMICONDUCTOR DEVICE WITH COPPER MIGRATION STOPPING OF A REDISTRIBUTION LAYER
A semiconductor device having a redistribution layer and a first coating layer. The redistribution layer is formed on a passivation layer of the semiconductor...
2018/0174991 Core Material, Semiconductor Package, and Forming Method of Bump Electrode
A core material including a core and a solder plating layer of a (Sn--Bi)-based solder alloy made of Sn and Bi on a surface of the core. Bi in the solder...
2018/0174990 METHOD FOR FORMING BUMP OF SEMICONDUCTOR PACKAGE
The present invention provides a method for forming bumps of a semiconductor package to suppress a final height difference between main bumps and support bumps...
2018/0174989 METHOD FOR PRODUCING SOLDERED ELECTRODE AND USE THEREOF
The present disclosure relates to a production process for a solder electrode, including a step (1) of forming a coating film of a photosensitive resin...
2018/0174988 CORROSION RESISTANT ALUMINUM BOND PAD STRUCTURE
A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al--Cu) layer over a dielectric layer; and depositing an ...
2018/0174987 SEMICONDUCTOR DEVICE
A semiconductor device is provided that includes a semiconductor chip having a main terminal and a control terminal, a main connection pin electrically...
2018/0174986 POWER DEVICE
There is provided a power device capable of easily designing a switching circuit that takes measures against high frequency noise while maintaining a switching...
2018/0174985 SEMICONDUCTOR CHIP
According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a...
2018/0174984 Packaging Devices and Methods for Semiconductor Devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging...
2018/0174983 SEMICONDUCTOR DEVICE INCLUDING CORNER RECESS
A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor...
2018/0174982 INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP
An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the...
2018/0174981 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME
A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on...
2018/0174980 Thin Film Transistor and Manufacturing Method Thereof, Array Substrate, and Display Panel
A thin film transistor comprises an active layer; a light-protection layer disposed above the active layer and/or disposed beneath the active layer, the...
2018/0174979 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may...
2018/0174978 SEMICONDUCTOR DEVICE, METHOD OF POSITIONING SEMICONDUCTOR DEVICE, AND POSITIONING APPARATUS FOR SEMICONDUCTOR...
A semiconductor device includes: a semiconductor chip that has a first connection terminal for wiring connection; a substrate that has a second connection...
2018/0174977 PLANARIZED INTERLAYER DIELECTRIC WITH AIR GAP ISOLATION
A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the...
2018/0174976 TRANSIENT ELECTRONICS USING THERMORESPONSIVE MATERIALS
A composite element and methods of fabrication thereof are provided. The composite element can include a binder material and one or more electrical traces...
2018/0174975 SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING SAME
An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily...
2018/0174974 FAN-OUT SEMICONDUCTOR PACKAGE
The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a...
2018/0174973 MOUNTING SUBSTRATE AND ELECTRONIC APPARATUS
A mounting substrate according to an embodiment of the present technology includes: a wiring substrate (30); a fine L/S layer (40) formed in contact with a top...
2018/0174972 CONDUCTIVE COATING FOR A MICROELECTRONICS PACKAGE
Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a...
2018/0174971 SEMICONDUCTOR MEMORY DEVICE
A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an...
2018/0174970 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer...
2018/0174969 SELF-ALIGNED VERTICAL TRANSISTOR WITH LOCAL INTERCONNECT
A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located...
2018/0174968 Source-Gate Region Architecture in a Vertical Power Semiconductor Device
A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked...
2018/0174967 POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and...
2018/0174966 SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the...
2018/0174965 DEVICES AND METHODS OF COBALT FILL METALLIZATION
Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an...
2018/0174964 INDUCTIVE CONNECTION STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT
A pad forms a connection terminal suitable for coupling circuit elements integrated in a chip to circuits outside the chip itself. At least one inductor is...
2018/0174963 Conductive Structure and Method of Forming the Same
Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be...
2018/0174962 INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF
An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, and a second dielectric layer. The first conductor is...
2018/0174961 Air Gap Structure and Method
A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first...
2018/0174960 MEMORY DEVICES, SEMICONDUCTOR DEVICES AND RELATED METHODS
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
2018/0174959 MEMORY DEVICE AND METHOD OF DISPOSING CONDUCTION LINES OF THE SAME
A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell...
2018/0174958 SEMICONDUCTOR DEVICE
A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and...
2018/0174957 METHOD OF FORMING INTERCONNECTION STRUCTURE
A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the...
2018/0174956 METHOD FOR MANUFACTURING INTERCONNECTION
A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric...
2018/0174955 MULTI-LAYER STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME AND A CORRESPONDING CONTACT STRUCTURE
A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and...
2018/0174954 WIRING STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
A wiring structure includes a main body, a first dielectric layer, a first circuit layer and a second dielectric layer. The first dielectric layer is disposed...
2018/0174953 METHOD OF DESIGNING A LAYOUT OF A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE INCLUDING A FIN
A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins. A contact plug is positioned on...
2018/0174952 SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICE HAVING THE SAME
A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base...
2018/0174951 SEMICONDUCTOR DEVICE AND METHOD WITH CLIP ARRANGEMENT IN IC PACKAGE
Various example embodiments concern an integrated circuit (IC) package having a clip with a protruding tough-shaped finger portion. The clip can be used in...
2018/0174950 Method Of Making A Wire Support Leadframe For A Semiconductor Device
A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of...
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