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Patent # Description
2018/0174949 METAL CORED SOLDER DECAL STRUCTURE AND PROCESS
A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more...
2018/0174948 INTEGRATED CIRCUIT CHIP WITH MOLDING COMPOUND HANDLER SUBSTRATE AND METHOD
Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an...
2018/0174947 POWER ELECTRONICS ASSEMBLY INCLUDING A CIRCUIT CARRIER
A circuit carrier for holding at least one electrical power component is disclosed. The circuit carrier including a heat sink for holding and for cooling the...
2018/0174946 Power Semiconductor Packages Having a Substrate with Two or More Metal Layers and One or More Polymer-Based...
Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the...
2018/0174945 POWER MODULE HAVING DUAL-SIDED COOLING
A power module having dual-sided cooling is provided with a semiconductor chip between an upper board and a lower board of the power module. In particular, the...
2018/0174944 HEAT TRANSFER STRUCTURE AND MANUFACTURING METHOD THEREFORE
Provided are (i) a heat transport structure which is excellent in heat transfer efficiency and (ii) a method of producing such a heat transport structure. The...
2018/0174943 SEMICONDUCTOR DIE ASSEMBLY HAVING HEAT SPREADER THAT EXTENDS THROUGH UNDERLYING INTERPOSER AND RELATED TECHNOLOGY
A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the...
2018/0174942 Power Module of Square Flat Pin-Free Packaging Structure
A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power...
2018/0174941 SEMICONDUCTOR MEMORY DEVICE AND A CHIP STACK PACKAGE HAVING THE SAME
A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the...
2018/0174940 FINE-FEATURED TRACES FOR INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES
Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a...
2018/0174939 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first semiconductor chip including an electrode pad on one surface of the first semiconductor chip; a multilayer chip stack...
2018/0174938 SEMICONDUCTOR DEVICE
Semiconductor device 1000 includes semiconductor 102, an electric field relaxation structure, at least one surface electrode 112, passivation layer 114, and...
2018/0174937 Info Structure with Copper Pillar Having Reversed Profile
A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first...
2018/0174936 Power Semiconductor Modules with Protective Coating
A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The...
2018/0174935 Semiconductor package and method for fabricating a semiconductor package
A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the...
2018/0174934 POWER CONVERTING DEVICE
In a power converting device, an anode lead plate and a cathode lead plate are disposed opposed in an interior of an insulating plate, whereby the respective...
2018/0174933 SCRIBE LANE STRUCTURE IN WHICH PAD INCLUDING VIA HOLE IS ARRANGED ON SAWING LINE
A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been...
2018/0174932 TRANSFER PRINTED DEVICE REPAIR
A repaired transfer printed system (e.g., micro-transfer printed system) includes a system substrate having two or more contact pads disposed on the system...
2018/0174931 LIGHT EMITTING DIODE (LED) TEST APPARATUS AND METHOD OF MANUFACTURE
Embodiments relate to functional test methods useful for fabricating products containing Light Emitting Diode (LED) structures. In particular, LED arrays are...
2018/0174930 METHOD FOR TESTING BRIDGING IN ADJACENT SEMICONDUCTOR DEVICES AND TEST STRUCTURE
Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first...
2018/0174929 SEMICONDUCTOR MANUFACTURING DEVICE, SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
According to one embodiment, provided is a semiconductor manufacturing device including a probe card arranged to face a semiconductor chip to be measured,...
2018/0174928 MOUNTING APPARATUS
A mounting apparatus is provided which includes a frame having a table, a support member disposed on the table to support a substrate, and a feeder mounted on...
2018/0174927 Contacts in Semiconductor Devices
An example embodiment relates to a method for making a contact to a source or drain region of a semiconductor device. The method may include providing the...
2018/0174926 Semiconductor Devices Comprising Nitrogen-Doped Gate Dielectric, and Methods of Forming Semiconductor Devices
Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The...
2018/0174925 Structure and Formation Method of Semiconductor Device Structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
2018/0174924 FABRICATION TECHNOLOGY FOR METAL GATE
One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer...
2018/0174923 METHODS FOR FABRICATING METAL GATE STRUCTURES
One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate...
2018/0174922 FinFET Structures and Methods of Forming the Same
A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a...
2018/0174921 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a substrate, including a first region and a second...
2018/0174920 SEMICONDUCTOR DEVICES
A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between...
2018/0174919 Dual Epitaxial Growth Process for Semiconductor Device
A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first...
2018/0174918 FINFET DEVICES AND METHODS OF FORMING
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a...
2018/0174917 FinFET Structures and Methods of Forming the Same
An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first...
2018/0174916 Gate Structures with Various Widths and Method for Forming the Same
Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a...
2018/0174915 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH METAL GATE ETCH SELECTIVITY CONTROL
A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy...
2018/0174914 MULTI-DEPTH ETCHING IN SEMICONDUCTOR ARRANGEMENT
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed...
2018/0174913 Semiconductor Device and Method
A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain...
2018/0174912 SEMICONDUCTOR DEVICE HAVING MERGED EPITAXIAL FEATURES WITH ARC-LIKE BOTTOM SURFACE AND METHOD OF MAKING THE SAME
A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate,...
2018/0174911 RAMO4 SUBSTRATE, AND METHOD FOR PRODUCING GROUP III NITRIDE CRYSTALS
An RAMO.sub.4 substrate that includes an RAMO.sub.4 monocrystalline substrate formed of a single crystal represented by general formula RAMO.sub.4, wherein R...
2018/0174910 ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES
A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the...
2018/0174909 HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING
A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an...
2018/0174908 MANUFACTURING PROCESS OF ELEMENT CHIP
A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing...
2018/0174907 SEMICONDUCTOR WAFER DICING METHOD
A method of dicing a bowed or warped semiconductor wafer includes cutting along the saw streets in a first direction on a first half of the wafer, where the...
2018/0174906 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND STACKED SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate; a through silicon via which penetrates the semiconductor substrate; an insulating film which is...
2018/0174905 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive...
2018/0174904 Self-Aligned Spacers and Method Forming Same
A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled...
2018/0174903 SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically...
2018/0174902 CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTEMS,...
Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device...
2018/0174901 CHAMBER CONDITIONING FOR REMOTE PLASMA PROCESS
The methods, systems and apparatus described herein relate to chamber conditioning for remote plasma processes, in particular remote nitrogen-based plasma...
2018/0174900 SEMICONDUCTOR DEVICE HAVING A DISCONTINUED PART BETWEEN A FIRST INSULATING FILM AND SECOND INSULATING FILM
A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a...
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