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Patent # Description
2018/0181538 DISTRIBUTABLE MODEL WITH DISTRIBUTED DATA
A system for improving a distributable model with distributed data is provided, comprising a network-connected distributable model source configured to serve...
2018/0181537 MULTITEMPORAL DATA ANALYSIS
A system for multitemporal data analysis is provided, comprising a directed computation graph service module configured to receive input data from a plurality...
2018/0181536 CPU INTERCONNECT APPARATUS AND SYSTEM, AND CPU INTERCONNECT CONTROL METHOD AND CONTROL APPARATUS
The present application discloses a CPU interconnect apparatus and system, and a CPU interconnect control method and control apparatus. The CPU interconnect...
2018/0181535 CALCULATING DEVICE, CALCULATING METHOD, AND COMPUTER READABLE RECORDING MEDIUM
A calculating device includes a key input unit, a display and a processor. The processor performs: calculating a payment data item from input calculation data...
2018/0181534 CALCULATION APPARATUS, DISPLAYING METHOD IN CALCULATION APPARATUS, AND RECORDING MEDIUM
A calculation apparatus in which a controlling unit performs a first storing process for storing a first value in a storing unit; a first displaying process...
2018/0181533 ENDING WRITE DATA TRANSFER IN I3C HDR-DDR MODE
Systems, methods, and apparatus are described that enable communication of flow-control signals over a serial bus. A method performed at a device coupled to...
2018/0181532 DATA TRANSFER ENDING IN PHASE DIFFERENTIAL MODES
Systems, methods, and apparatus are described that enable communication of flow-control signals over a serial bus that is operated in a phase differential mode...
2018/0181531 SERIAL PERIPHERAL MODE IN MIPI IMPROVED INTER-INTEGRATED CIRCUIT (I3C)
Embodiments of the present disclosure may relate to an I3C bus master that is to identify that an I3C bus with which the I3C bus master is coupled is to enter...
2018/0181530 Techniques for Coalescing Doorbells in a Request Message
Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are...
2018/0181529 RING NETWORK SYSTEM USING PERIPHERAL COMPONENT INTERCONNECT EXPRESS AND SETTING METHOD THEREOF
A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe...
2018/0181528 CONTROLLER CIRCUIT AND METHOD FOR ESTIMATING TRANSMISSION DELAY
A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing...
2018/0181527 Techniques for Dynamically Modifying Platform Form Factors of a Mobile Device
Examples include techniques for dynamically modifying a platform form factor of a mobile device. In some examples, a system may include a split memory array...
2018/0181526 Virtual General Purpose Input/Output For A Microcontroller
A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of...
2018/0181525 BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch...
2018/0181524 INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit...
2018/0181523 ADJUSTMENT OF BUFFER CREDITS AND OTHER PARAMETERS IN A STARTUP PHASE OF COMMUNICATIONS BETWEEN A PLURALITY OF...
A control unit provides a number of buffer credits, to one or more channels, in response to an initiation of a startup phase of communication between the one...
2018/0181522 MODULAR COMMAND DEVICE FOR ELECTROVALVE ISLANDS
A modular command device for electrovalve islands having: an input module selected from an input module of the parallel type or the serial type having an input...
2018/0181521 SYSTEMS AND METHODS FOR FLIPPING NIC TEAMING CONFIGURATION WITHOUT INTERFERING LIVE TRAFFIC
Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the...
2018/0181520 SYSTEM ON CHIP HAVING INTEGRATED SOLID STATE GRAPHICS CONTROLLERS
Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s))...
2018/0181519 METHOD AND APPARATUS FOR ACCESSING NON-VOLATILE MEMORY AS BYTE ADDRESSABLE MEMORY
Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable...
2018/0181518 APPARATUS FOR CONNECTING NON-VOLATILE MEMORY LOCALLY TO A GPU THROUGH A LOCAL SWITCH
Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first...
2018/0181517 DISCOVERY MECHANISMS FOR UNIVERSAL SERIAL BUS (USB) PROTOCOL ADAPTATION LAYER
A WiFi serial bus (WSB) attribute for use in Wi-Fi Alliance defined point-to-point (P2P) discovery mechanism includes a plurality of fields disposed in the...
2018/0181516 PROGRAMMING INTERFACE OPERATIONS IN A DRIVER IN COMMUNICATION WITH A PORT FOR REINITIALIZATION OF STORAGE...
A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is...
2018/0181515 SERIAL BUS ELECTRICAL TERMINATION CONTROL
Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first...
2018/0181514 MULTI-DEVICE DATA STORAGE MODULE
A data storage system can employ one or more data storage modules that each have multiple constituent data storage devices. A plurality of data storage devices...
2018/0181513 DEVICE CONNECTED TO OTHER DEVICE BY SINGLE WIRE AND METHOD OF OPERATING SYSTEM INCLUDING THE DEVICES
Provided are a device connected to another device by a single wire and a method of operating a system including the devices. The method of operating the device...
2018/0181512 SYNCHRONIZATION OF A NETWORK OF SENSORS
The invention relates to a system comprising a plurality of boards, each of which comprises a sensor and a control processor. The boards are connected together...
2018/0181511 DYNAMIC TERMINATION CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME
A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to...
2018/0181510 MEMORY CHANNEL SELECTION CONTROL
An apparatus comprising a first circuit, a second circuit and a channel decoder. The first circuit may comprise (i) a controller port and (ii) a plurality of...
2018/0181509 ELECTRONIC DEVICE AND METHOD FOR PREVENTING CORROSION TO CONNECTOR
An electronic device and method for communicating with an external electronic device that is connected via a connector of the electronic device are provided....
2018/0181508 SEMICONDUCTOR DEVICE
A semiconductor device is provided that can process various events while suppressing complication of logical configuration. The semiconductor device includes a...
2018/0181507 OUT-OF-BAND INTERRUPT MAPPING IN MIPI IMPROVED INTER-INTEGRATED CIRCUIT COMMUNICATION
Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I.sup.2C)...
2018/0181506 BUS TRAFFIC CONTROL APPARATUS AND BUS SYSTEM HAVING THE SAME
A bus traffic control apparatus includes a sizing block, a traffic request controller and a bus master engine. The sizing block is configured to determine a...
2018/0181505 PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a...
2018/0181504 APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELATIONS OF A MEMORY INTERFACE
The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and...
2018/0181503 DATA FLOW COMPUTATION USING FIFOS
Disclosed embodiments provide techniques for data manipulation with logic circuitry. One or more processing elements are reconfigured in a connected topology....
2018/0181502 LOW LATENCY RETIMER
A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second...
2018/0181501 MEMORY WRITE PROTECTION FOR MEMORY CORRUPTION DETECTION ARCHITECTURES
Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method...
2018/0181500 TAMPER-PROOF STORAGE USING SIGNATURES BASED ON THRESHOLD VOLTAGE DISTRIBUTIONS
An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store...
2018/0181499 SECURE MEMORY
Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data...
2018/0181498 METHOD AND SYSTEM FOR CO-PRIVILEGED SECURITY DOMAINS
A system and method is provided for secure establishment of a trusted enclave among co-privileged executable code. The system comprises one or more processors;...
2018/0181497 INVOKING DEMOTE THREADS ON PROCESSORS TO DEMOTE TRACKS FROM A CACHE
Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote...
2018/0181496 CONFIGURABLE SKEWED ASSOCIATIVITY IN A TRANSLATION LOOKASIDE BUFFER
Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation...
2018/0181495 OPTIMIZED HOPSCOTCH MULTIPLE HASH TABLES FOR EFFICIENT MEMORY IN-LINE DEDUPLICATION APPLICATION
A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical...
2018/0181494 ELECTRONIC SYSTEM WITH MEMORY MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF
An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a...
2018/0181493 CACHE MEMORY DEVICE AND SEMICONDUCTOR DEVICE
A cache memory device includes: data memory that stores cache data corresponding to data in main memory; tag memory that stores tag information to identify the...
2018/0181492 WATERFALL COUNTERS AND AN APPLICATION TO ARCHITECTURAL VULNERABILITY FACTOR ESTIMATION
Described herein are waterfall counters and an application to architectural vulnerability factor (AVF) estimation. Waterfall counters count events that are...
2018/0181491 TARGETED CACHE FLUSHING
Techniques are disclosed relating to flushing cache lines. In some embodiments, a graphics processing unit includes a cache and one or more storage elements...
2018/0181490 SYSTEM AND METHOD FOR SELF-INVALIDATION, SELF-DOWNGRADE CACHECOHERENCE PROTOCOLS
Methods and systems for self-invalidating cachelines in a computer system having a plurality of cores are described. A first one of the plurality of cores,...
2018/0181489 Memory Consistency in Graphics Memory Hierarchy with Relaxed Ordering
Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level...
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