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Patent # Description
2018/0269180 METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE
The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size....
2018/0269179 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed is a semiconductor device that includes a semiconductor chip; bonding pads provided to the semiconductor chip; a plurality of lead terminals arranged...
2018/0269178 WAFER BONDING METHODS AND WAFER-BONDED STRUCTURES
A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a...
2018/0269177 METAL BONDING PADS FOR PACKAGING APPLICATIONS
Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured...
2018/0269176 ANISOTROPIC ELECTRICALLY CONDUCTIVE FILM
An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an...
2018/0269175 Thermal Bonding Sheet and Thermal Bonding Sheet with Dicing Tape
A thermal bonding sheet includes a layer, in which hardness of the layer after being heated at a heating rate of 1.5.degree. C./sec from 80.degree. C. to...
2018/0269174 ADHESIVE BONDING COMPOSITION AND ELECTRONIC COMPONENTS PREPARED FROM THE SAME
A curable resin or adhesive composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to...
2018/0269173 FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER
Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer...
2018/0269172 Multi-metal contact structure
A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and...
2018/0269171 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon...
2018/0269170 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a...
2018/0269169 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the...
2018/0269168 MODULE SUBSTRATE
A module substrate includes a surface layer to which a rectangular waveguide structure having a waveguide aperture is to be connected; metal layers stacked...
2018/0269167 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding...
2018/0269166 SEMICONDUCTOR DEVICE
A semiconductor device includes a metal member (15), a first semiconductor chip (13), a second semiconductor chip (14), a first solder (24) and a second solder...
2018/0269165 SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a single inline package with high vibration resistance. External terminals (2a to 2c) are extracted from a resin...
2018/0269164 SEMICONDUCTOR PACKAGE STRUCTURE
A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite...
2018/0269163 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing...
2018/0269162 SEMICONDUCTOR DEVICE
There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost...
2018/0269161 METAL LINE DESIGN FOR HYBRID-BONDING APPLICATION
A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor...
2018/0269160 Semiconductor device package with a stress relax pattern
A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically...
2018/0269159 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes; bonding a plurality of semiconductor chips to a plurality of mounting regions on a wiring board...
2018/0269158 SEMICONDUCTOR PACKAGES HAVING WIRE BOND WALL TO REDUCE COUPLING
A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an...
2018/0269157 WIRING, SEMICONDUCTOR DEVICE AND NAND FLASH MEMORY
A wiring of an embodiment includes: a multilayer graphene including graphene sheets laminated in a first direction, the multilayer graphene extended in a...
2018/0269156 ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME
An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and...
2018/0269155 BODY-BIAS VOLTAGE ROUTING STRUCTURES
Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an...
2018/0269154 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
The present disclosure can reduce power consumption of a semiconductor integrated circuit device using a power interruption technique, without increasing the...
2018/0269153 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated...
2018/0269152 POWER RAIL FOR STANDARD CELL BLOCK
A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating...
2018/0269151 Semiconductor Device and Method
A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and...
2018/0269150 METAL INTERCONNECTS FOR SUPER (SKIP) VIA INTEGRATION
The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and...
2018/0269149 MEMORY DEVICE
The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric...
2018/0269148 SEMICONDUCTOR DEVICE, LAYOUT PATTERN AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT
A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The...
2018/0269147 METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE
A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive...
2018/0269146 Die Embedding
A power semiconductor device package includes a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die...
2018/0269145 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate;...
2018/0269143 LATERAL VIAS FOR CONNECTIONS TO BURIED MICROCONDUCTORS AND METHODS THEREOF
The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through...
2018/0269142 SUBSTRATE CONSTRUCTION AND ELECTRONIC PACKAGE INCLUDING THE SAME
The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a...
2018/0269141 CHIP-SIZE, DOUBLE SIDE CONNECTION PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post...
2018/0269140 SEMICONDUCTOR DEVICE
A lead frame extends from inside a sealing resin to outside the sealing resin, and is placed to make contact with a main surface of an insulating sheet...
2018/0269139 PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is...
2018/0269138 PACKAGED SEMICONDUCTOR DEVICES WITH LASER GROOVED WETTABLE FLANK AND METHODS OF MANUFACTURE
In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a...
2018/0269137 LEAD FRAME
A lead frame includes: a plurality of units each including a first lead portion and a second lead portion arranged in a first direction, wherein the units are...
2018/0269136 ELECTRONIC DEVICE
An electronic device includes: a base; a wiring pattern formed on the base; an electronic element disposed on the wiring pattern; and a bonding layer...
2018/0269135 METHODS AND APPARATUS FOR AN IMPROVED INTEGRATED CIRCUIT PACKAGE
In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to...
2018/0269134 APPARATUS AND METHOD OF THREE DIMENSIONAL CONDUCTIVE LINES
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a...
2018/0269133 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to an embodiment includes a semiconductor substrate including a first face having semiconductor elements, and a second face on...
2018/0269132 SEMICONDUCTOR DEVICE
A semiconductor device (100) comprises a main body portion (50), a semiconductor element (51), a sealing portion (60) and a first lead (10). The first lead...
2018/0269131 COMPONENT COOLING SYSTEM
Technology is provided for a component cooling system. The system can include a cooling block assembly and a radiator. The cooling block assembly includes a...
2018/0269130 Satellite communication transmitter with improved thermal management
A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF...
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