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Patent # Description
2018/0268927 METHOD FOR CONSTRUCTING CLOUD INTEGRATION AND MANAGEMENT SYSTEM CAPABLE OF INTERACTIVELY OPERATING AND USING...
A method for constructing a cloud integration and management system capable of interactively operating and using medical information is disclosed. The method...
2018/0268926 MEDICAL DATA SYSTEM AND METHOD
The present application regards a system and method including database(s) of medical records, processed medical records, user profile information and...
2018/0268925 METHOD FOR INTEGRATING DIAGNOSTIC DATA
A method for integrating diagnostic data, includes steps of: reading a plurality of medical records each including an identity information and a medical...
2018/0268924 METHODS FOR LABORATORY SAMPLE TRACKING AND DEVICES THEREOF
A method of managing and tracking a collected laboratory sample includes receiving a patient identifier and laboratory-workflow information related to the...
2018/0268923 BIOMETRIC CONFIRMATION OF SAMPLE INTEGRITY
Provided herein are new methods and systems to remotely administer toxicology tests while still preserving the chain of custody. These tea,methods and systems...
2018/0268922 Methods for Improving the Clinical Outcome of Patient Care and for Reducing Overall Health Care Costs
System and method for reducing healthcare costs by improving care and encouraging healthy behaviors. A web-based or telephonic program using health plan...
2018/0268921 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
A nonvolatile memory device includes a memory cell array and a bad block remapping circuit. The memory cell array includes a first mat and a second mat that...
2018/0268920 SCREENING METHOD FOR MAGNETIC STORAGE DEVICE, SCREENING APPARATUS FOR MAGNETIC STORAGE DEVICE, AND...
According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in...
2018/0268919 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
An operating method for a data storage device may include: determining a displacement value based on section memory cell numbers regarding a plurality of...
2018/0268918 SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION OF AN INTERFACE WITHIN A CIRCUIT
A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an...
2018/0268917 MEMORY DEVICE AND TEST METHOD THEREOF
A test method for a memory device may include: performing a first write operation of writing test data to first regions of a normal cell region and a parity...
2018/0268916 PAD DETECTION THROUGH PATTERN ANALYSIS
A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example,...
2018/0268915 BOARD LEVEL LEAKAGE TESTING FOR MEMORY INTERFACE
Embodiments are generally directed to board level leakage testing for a memory interface. An embodiment of an apparatus includes multiple logic cells for...
2018/0268914 SHIFT REGISTER, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS
The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit,...
2018/0268913 REMAPPING OPERATIONS
A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory...
2018/0268912 Flash Memory Array With Individual Memory Cell Read, Program and Erase
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory...
2018/0268911 MEMORY CARD
A memory card is provided to include a substrate having two pairs of edges facing each other, a plurality of first row terminals that are arranged adjacent to...
2018/0268910 MEMORY SYSTEM
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile...
2018/0268909 MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
2018/0268908 MEMORY SYSTEM
According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a...
2018/0268907 NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD OF THE SAME
A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes...
2018/0268906 MEMORY DEVICE AND MEMORY CONTROLLER
According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines...
2018/0268905 SPLIT MEMORY BANK
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the...
2018/0268904 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH A PLURALITY OF MEMORY BLOCKS AND A SHARED BLOCK DECODER
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has...
2018/0268903 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME
A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy...
2018/0268902 STORAGE DEVICE
A storage device includes a circuit on a substrate, electrode layers stacked on the circuit, a channel layer penetrating the electrode layers in a stacking...
2018/0268901 METHOD FOR WRITING IN AN EEPROM MEMORY AND CORRESPONDING DEVICE
A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory...
2018/0268900 Data Storage with In-situ String-Searching Capabilities Comprising Three-Dimensional Vertical...
A preferred data storage with in-situ string-searching capabilities comprises a plurality of storage-processing units (SPU), with each SPU comprising at least...
2018/0268899 ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime...
2018/0268898 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit...
2018/0268897 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors...
2018/0268896 MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES
The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include...
2018/0268895 Method and Circuit to Enable Wide Supply Voltage Difference in Multi-Supply Memory
A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving...
2018/0268894 Skewed Corner Tracking for Memory Write Operations
A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy...
2018/0268893 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory...
2018/0268892 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines...
2018/0268891 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
A semiconductor memory device includes a memory cell transistor, a word line coupled to the memory cell transistor, a temperature detection element configured...
2018/0268890 REFRESH-FREE TFET MEMORY LATCH
Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET;...
2018/0268889 MAGNETIC MEMORY DEVICE WITH ENHANCED WRITE PERFORMANCE AND OPERATION METHOD THEREOF
A magnetic memory device includes a magnetic element and a write circuit electrically connected to two nodes of the magnetic element and configured to provide...
2018/0268888 MAGNETIC MEMORY DEVICE
According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer,...
2018/0268887 MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY
A magnetoresistive element according to an embodiment includes: a first nonmagnetic layer; a first magnetic layer; a second magnetic layer disposed between the...
2018/0268886 MAGNETIC MEMORY
A magnetic memory of an embodiment includes: first through third terminals; a conductive layer including first through third portions, the first portion being...
2018/0268885 MEMORY CIRCUIT
A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when...
2018/0268884 SEMICONDUCTOR DEVICES
A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a...
2018/0268883 DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION
The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein...
2018/0268882 Memory Controllers, Systems, and Methods Supporting Multiple Request Modes
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over...
2018/0268881 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME
In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller...
2018/0268880 SEMICONDUCTOR MEMORY DEVICE, FLAG GENERATING CIRCUIT, AND METHOD OF OUTPUTTING DATA IN A SEMICONDUCTOR DEVICE
A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of...
2018/0268879 SEMICONDUCTOR DATA MULTIPLEXER CIRCUIT
A semiconductor device includes a data output selection circuit suitable for outputting first pattern data as selection data in the case where a training...
2018/0268877 SEMICONDUCTOR STORAGE DEVICE
According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first...
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