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Patent # Description
2018/0277205 MEMORY DEVICE AND CONTROL METHOD THEREOF
A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third...
2018/0277204 MEMORY SYSTEM
A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a...
2018/0277203 STORAGE DEVICE AND CONTROL METHOD THEREOF
A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is...
2018/0277202 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed...
2018/0277201 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a...
2018/0277200 METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA
Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a...
2018/0277199 SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS
A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power...
2018/0277198 SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING THE SAME
A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate...
2018/0277197 SRAM CELL
A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access...
2018/0277196 DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY AND OUTPUT DRIVING CIRCUIT THEREOF
A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first...
2018/0277195 DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the...
2018/0277194 TIMING CONTROL FOR INPUT RECEIVER
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information...
2018/0277193 MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe...
2018/0277192 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film,...
2018/0277191 FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench...
2018/0277190 THERMALLY-ASSISTED SPIN TRANSFER TORQUE MEMORY WITH IMPROVED BIT ERROR RATE PERFORMANCE
Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material...
2018/0277189 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having...
2018/0277188 MEMORY DEVICE
According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a...
2018/0277187 COMPUTER SYSTEM AND MEMORY DEVICE
According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read...
2018/0277186 MEMORY DEVICE
According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a...
2018/0277185 MAGNETIC MEMORY DEVICE
According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer,...
2018/0277184 Data writing method of magnetic memory
A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom...
2018/0277183 MEMORY DEVICE
According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area...
2018/0277182 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first...
2018/0277181 MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more...
2018/0277180 MEMORY SYSTEM
A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in...
2018/0277179 EMBEDDED MEMORY WITH SETUP-HOLD TIME CONTROLLED INTERNALLY OR EXTERNALLY AND ASSOCIATED INTEGRATED CIRCUIT
An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal,...
2018/0277178 SEMICONDUCTOR DEVICE
A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a...
2018/0277177 MEMORY DEVICE AND MEMORY SYSTEM
According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read...
2018/0277176 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: a memory device; and a controller suitable for controlling the memory device to perform a serial read operation by providing a serial...
2018/0277175 SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch...
2018/0277174 Address Fault Detection In A Flash Memory System
A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an...
2018/0277173 CONTROL SYSTEM
According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller...
2018/0277172 MEMORY MODULE INCLUDING BATTERY
A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or...
2018/0277171 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory...
2018/0277170 SEMICONDUCTOR DEVICE AND ELECTRONIC EQUIPMENT
According to one embodiment, a semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first...
2018/0277169 DISK APPARATUS
A disk apparatus includes a base including a bottom wall and a sidewall disposed along a peripheral portion of the bottom wall, a cover including a ceiling...
2018/0277168 DISK DEVICE AND METHOD OF MANUFACTURING DISK DEVICE
According to one embodiment, a disk device includes a disk-shaped recording medium, a head which processes data on the recording medium, and a housing...
2018/0277167 VIDEO REPRODUCTION DEVICE AND METHOD
A video reproduction device includes a store computer configured to acquire a video data from a video data storage device. The video data is from multiple...
2018/0277165 Non-Greedy Hierarchical Segmentation of Serial Data.
Segmenting serial data by processing multiple candidate segmentation point sets associated with a serial data set, each candidate set including a different...
2018/0277164 SIGNALLING OF VIDEO CONTENT INCLUDING SUB-PICTURE BITSTREAMS FOR VIDEO CODING
In various implementations, modifications and/or additions to the ISOBMFF are provided to process video data. A plurality of sub-picture bitstreams are...
2018/0277163 IMAGE DECODING DEVICE, IMAGE DECODING METHOD, IMAGE ENCODING DEVICE, AND IMAGE ENCODING METHOD
Provided is an image decoding device including an acquisition unit configured to acquire clean random access (CRA) information used to identify one or more CRA...
2018/0277162 PRINTER
The disclosure discloses a printer including a memory storing computer-executable instructions. When the instruction is executed by a processor, a printer...
2018/0277161 Accessing a Video Segment
A method comprising: causing provision of a visual access menu to enable a user to access video segments of a scene comprising: causing display of at least a...
2018/0277160 TRACK PLAYBACK CONTROLLING APPARATUS
A track playback controlling apparatus includes at least one operation receiver, a driver, and a processor. The operation receiver receives operation to change...
2018/0277159 RADIATION IMAGE DISPLAY APPARATUS AND RADIATION IMAGE PHOTOGRAPHING SYSTEM
A radiation image display apparatus that includes: a hardware processor that generates the moving image for preview based on the pieces of image data of the...
2018/0277158 STORAGE DEVICE AND CONTROLLER
A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for...
2018/0277157 SELECTIVE INDEX WRITING PRIOR TO UNTHREADING A MAGNETIC RECORDING TAPE
A drive-implemented method according to one embodiment includes determining that unthreading of a tape is to be performed, and in response to the determination...
2018/0277156 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM
Data reproduction is performed in a mode decided on the basis of disc type information which is record data of a disc. A reading rate compatible with a...
2018/0277155 ASYNCHRONOUS ASYMMETRY COMPENSATION FOR DATA READ FROM A STORAGE MEDIUM
A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith, wherein...
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