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Patent # Description
2018/0287003 SOLAR CELL AND METHOD OF MANUFACTURING SOLAR CELL
A solar cell includes: a crystalline semiconductor substrate of a first conductivity type or a second conductivity type; an amorphous layer provided on a...
2018/0287002 HIGH VOLTAGE PHOTOVOLTAICS WITH STACKED MULTI-JUNCTIONS USING WIDE BANDGAP MATERIALS
A photovoltaic device including a first cell positioned at a light receiving end of the photovoltaic device. The first cell has a first sequence of first...
2018/0287001 HIGH VOLTAGE PHOTOVOLTAICS WITH STACKED MULTI-JUNCTIONS USING WIDE BANDGAP MATERIALS
A photovoltaic device including a first cell positioned at a light receiving end of the photovoltaic device. The first cell has a first sequence of first...
2018/0287000 PARABOLIC CONCENTRATOR INTEGRATED WITH BALL LENS
A solar concentrator apparatus for harnessing solar flux is disclosed. The solar concentrator apparatus has a parabolic body having a reflecting surface to...
2018/0286999 SOLAR CELL MODULE AND SOLAR CELL MODULE MANUFACTURING METHOD
A solar cell module is provided with: a plurality of solar cell elements each having a surface; a light diffusion portion provided in an outer peripheral area...
2018/0286998 Mechanical Matrix for Enhancing the Thermomechanical and Chemical Reliability of Optoelectronic Device Technologies
Mechanical scaffolds within optoelectronic devices are provided to enhance the overall thermomechanical and chemical stability of these devices. For example,...
2018/0286997 ENCAPSULANT FOR SOLAR CELLS AND SOLAR CELL MODULE COMPRISING THE SAME
Embodiments relate to an encapsulant for solar cells and a solar cell module comprising the same. The encapsulant for solar cells is excellent in moisture...
2018/0286996 REDUCED JUNCTION AREA BARRIER-BASED PHOTODETECTOR
A photodetector structure having a barrier layer disposed between a pair of like-conductively doped semiconductor layers, the barriers layer having a surface...
2018/0286995 DEPOSITION APPROACHES FOR EMITTER LAYERS OF SOLAR CELLS
Methods of fabricating solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a...
2018/0286994 WIRE-BASED METALLIZATION FOR SOLAR CELLS
Approaches for fabricating wire-based metallization for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a...
2018/0286993 ELECTRODE ARRANGEMENT AND METHOD OF PRODUCTION THEREOF
A method for use in producing an electrode arrangement is described. The method comprises providing a first patterned structure, said first patterned structure...
2018/0286992 METHOD OF PROCESSING INCONSISTENCIES IN SOLAR CELL DEVICES AND DEVICES FORMED THEREBY
The present disclosure is directed to a method of processing a solar cell device. The method comprises detecting at least one inconsistency at a surface of a...
2018/0286991 COATED FOIL-BASED METALLIZATION OF SOLAR CELLS
Coated foil-based approaches for metallization of solar cells, and the resulting solar cells, are described. For example, a solar cell includes a substrate. A...
2018/0286990 SEMICONDUCTOR DEVICE HAVING RESISTANCE VOLTAGE DIVIDING CIRCUIT
All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type...
2018/0286989 THIN FILM TRANSISTOR AND METHOD FOR DETECTING PRESSURE BY UTILIZING THE SAME AND TOUCH APPARATUS
A thin film transistor and a method for detecting a pressure by utilizing the thin film transistor, and a touch apparatus are provided. The thin film...
2018/0286988 FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A ferroelectric memory device includes a substrate having a source region and a drain region, a first ferroelectric material layer and a second ferroelectric...
2018/0286987 NONVOLATILE MEMORY DEVICE
A ferroelectric memory device is disclosed. The ferroelectric memory device includes a substrate, an indium-gallium-zinc oxide layer disposed on the substrate,...
2018/0286986 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor...
2018/0286985 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SAME
A semiconductor device includes a thin film transistor including an oxide semiconductor layer and a wire connecting portion (201). The wire connecting portion...
2018/0286984 Semiconductor Device with Reduced Parasitic Capacitance
A semiconductor device comprising a substrate and a transistor comprising a source, drain, and gate formed on the substrate. The semiconductor device further...
2018/0286982 FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE
The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances...
2018/0286981 SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW RDSON AND MANUFACTURING METHOD THEREOF
A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate...
2018/0286980 VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON A SUBSTRATE WITH VARYING EFFECTIVE GATE LENGTHS
A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on...
2018/0286979 METHOD FOR MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE
A step of forming a silicon carbide substrate includes steps of: forming a first impurity region having a first conductivity type by epitaxial growth; forming...
2018/0286978 VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the...
2018/0286977 VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the...
2018/0286976 LATERALLY DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity...
2018/0286975 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a...
2018/0286974 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and...
2018/0286973 HIGH FREQUENCY DEVICE
A high frequency device includes a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer,...
2018/0286972 Aluminum-rich field-plated nitride transistors for record high currents
New Nitride semiconductor epitaxy incorporating high Aluminum content is presented. It incorporated traces of Indium that adequately tuned its lattice size...
2018/0286971 IGBT with dV/dt Controllability
An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier...
2018/0286970 SEMICONDUCTOR DEVICE
A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a...
2018/0286969 AMBIPOLAR TRANSISTOR AND ELECTRONIC SENSOR OF HIGH SENSITIVITY USING THE SAME
Disclosed are an ambipolar transistor and a high-sensitivity electronic sensor using the same. The ambipolar transistor includes: a substrate; a gate formed on...
2018/0286968 SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS WITH A BASE GROWN IN A DIELECTRIC CAVITY
Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a...
2018/0286967 PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH
A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D...
2018/0286966 METHOD OF FORMING SEMICONDUCTOR FIN STRUCTURE
A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between...
2018/0286965 METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING OPENING FILLED WITH INSULATOR IN METAL GATE
The disclosure is directed to methods of forming an integrated circuit structure. One method may include: forming a metal gate within a dielectric layer over a...
2018/0286964 VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE
A vertical Schottky diode includes an ohmic contact, a first epitaxial N-type gallium nitride layer physically contacting the ohmic contact and having a first...
2018/0286963 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying...
2018/0286962 CO-DOPING PROCESS FOR N-MOS SOURCE DRAIN APPLICATION
A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of...
2018/0286961 SELECTIVE PROCESS FOR SOURCE AND DRAIN FORMATION
A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of...
2018/0286960 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and...
2018/0286959 FINFET STRUCTURE WITH COMPOSITE GATE HELMET
A FinFET device includes a fin structure, a gate structure, a gate helmet, a pair of spacers and a contact structure. The fin structure protrudes from a...
2018/0286958 LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES
An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel...
2018/0286957 SEMICONDUCTOR DEVICE
A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating...
2018/0286956 METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION
One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a...
2018/0286955 SEMICONDUCTOR DEVICE
A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor...
2018/0286954 GROUP III - NITRIDE STRUCTURE HAVING SUCCESSIVELY REDUCED CRYSTALLOGRAPHIC DISLOCATION DENSITY REGIONS
A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure...
2018/0286953 SEMICONDUCTOR DEVICE, INVERTER CIRCUIR, AND VEHICLE
A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC...
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