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Patent # Description
2018/0286901 BACK-ILLUMINATED SOLID-STATE IMAGING ELEMENT
A back-illuminated solid-state imaging element includes a semiconductor substrate which has a front surface and a back surface provided with a recess, and in...
2018/0286900 SEMICONDUCTOR STRUCTURE, BACK-SIDE ILLUMINATED IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening;...
2018/0286899 METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE
A method of manufacturing an optical semiconductor device includes preparing a semiconductor substrate having a plurality of photoelectric conversion parts,...
2018/0286898 OPTICAL SEMICONDUCTOR DEVICE
An optical semiconductor device includes a semiconductor substrate having a plurality of photoelectric conversion parts and having a trench formed to separate...
2018/0286897 CROSS TALK REDUCTION FOR HIGH DYNAMIC RANGE IMAGE SENSORS
A multi-color HDR image sensor includes at least a first combination color pixel with a first color filter and an adjacent second combination color pixel with...
2018/0286896 IMAGE SENSOR
A substrate includes a plurality of pixels arranged in a two-dimensional array structure and has a front side and a back side opposite to the front side. An...
2018/0286895 CROSS TALK REDUCTION FOR HIGH DYNAMIC RANGE IMAGE SENSORS
A multi-color HDR image sensor includes at least a first combination color pixel with a first color filter and an adjacent second combination color pixel with...
2018/0286894 OPTICAL ISOLATION STRUCTURE FOR REDUCING CROSSTALK BETWEEN PIXELS AND FABRICATION METHOD THEREOF
An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric...
2018/0286893 TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is...
2018/0286892 DISPLAY DEVICE
According to one embodiment, a display device includes a pixel, a scanning line, a signal line, a pixel electrode, a first switching element, and a capacitance...
2018/0286891 THIN FILM TRANSISTOR AND DISPLAY DEVICE
In an exemplary embodiment of the present disclosure, a thin film transistor including a gate electrode, an active layer, a source electrode, and a drain...
2018/0286890 DISPLAY DEVICE
The purpose of the invention is to improve reliability of the TFT of the oxide semiconductor. The invention is characterized as follows. A display device...
2018/0286889 DISPLAY DEVICE
The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device...
2018/0286888 DISPLAY DEVICE
The purpose of the present invention is to realize the TFT of the oxide semiconductor having a superior characteristics and high reliability during the...
2018/0286887 DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
An object of the present invention is to decrease substantial resistance of an electrode such as a transparent electrode or a wiring, and furthermore, to...
2018/0286886 SEMICONDUCTOR DEVICE
A semiconductor device which can suppress leakage current between a wiring and a connection electrode connected to a floating node is provided. The...
2018/0286885 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for...
2018/0286884 CIRCUIT CELLS HAVING SEPARATED GATE ELECTRODES
A device includes first circuit cells. Each of the first circuit cells includes isolation transistors, a first type transistor, a second type transistor, and a...
2018/0286883 Methods of Forming Integrated Structures
Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include...
2018/0286882 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME
According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor...
2018/0286881 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF
In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control...
2018/0286880 NONVOLATILE STORAGE ELEMENT AND REFERENCE VOLTAGE GENERATION CIRCUIT
To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming...
2018/0286879 Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge...
An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a...
2018/0286878 ELECTRONIC CHIP MANUFACTURING METHOD
Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the...
2018/0286877 NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR PREVENTING NON-VOLATILE MEMORY STRUCTURE FROM GENERATING PROGRAM...
A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is...
2018/0286876 FLASH MEMORY CELLS, COMPONENTS, AND METHODS
Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one...
2018/0286875 MEMORY CELL, NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR...
When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high...
2018/0286874 CONDUCTIVE CHANNELS AND SOURCE LINE COUPLING
Conductive channel technology is disclosed. In one example, a memory component can include a source line, a conductive channel having first and second...
2018/0286873 DEVICES WITH CONTACT-TO-GATE SHORTING THROUGH CONDUCTIVE PATHS BETWEEN FINS AND FABRICATION METHODS
Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method...
2018/0286872 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an...
2018/0286871 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate with a...
2018/0286870 SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATE UPPER AND LOWER BIT LINE SPACERS
A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall,...
2018/0286869 VERTICAL GATE-ALL-AROUND TFET
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET...
2018/0286868 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME
A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a plurality of active areas, a shallow trench...
2018/0286867 METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE
A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a...
2018/0286866 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench...
2018/0286865 Semiconductor Constructions, and Semiconductor Processing Methods
Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces....
2018/0286864 SEMICONDUCTOR DEVICE
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when...
2018/0286863 INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME
The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a...
2018/0286862 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
A semiconductor device includes a first SiGe fin formed on a substrate and including a first amount of Ge, and a second SiGe fin formed on a substrate and...
2018/0286861 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a...
2018/0286860 CMOS COMPATIBLE LOW GATE CHARGE HIGH VOLTAGE PMOS
A split gate power transistor includes a laterally configured power PMOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the...
2018/0286859 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a...
2018/0286858 THREE DIMENSIONAL LVDMOS TRANSISTOR STRUCTURES
A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a...
2018/0286857 SEMICONDUCTOR DEVICE WITH SNUBBER AND ASSOCIATED FABRICATION METHOD
A semiconductor device having a dummy trench structure. The dummy trench structure vertically extends from the top surface of the semiconductor device through...
2018/0286856 CMOS COMPATIBLE FUSE OR RESISTOR USING SELF-ALIGNED CONTACTS
A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure...
2018/0286855 ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE
Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD...
2018/0286854 Method and Device for Electrical Overstress and Electrostatic Discharge Protection
A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically...
2018/0286853 HIGH SURGE TRANSIENT VOLTAGE SUPPRESSOR
A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche...
2018/0286852 HIGH SURGE BI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR
A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions...
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