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Patent # Description
2018/0286850 SEMICONDUCTOR DEVICE AND OPERATION METHOD OF THE SAME
To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate...
2018/0286849 DEEP HIGH CAPACITY CAPACITOR FOR BULK SUBSTRATES
A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon...
2018/0286848 DEEP HIGH CAPACITY CAPACITOR FOR BULK SUBSTRATES
A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon...
2018/0286847 Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device...
2018/0286846 HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)
A semiconductor device structure is provided. The semiconductor device structure includes a bonding structure formed between a first substrate and a second...
2018/0286845 POWER SEMICONDUCTOR MODULE FOR AN INVERTER CIRCUIT AND METHOD OF MANUFACTURING THE SAME
A semiconductor device according to the present invention incudes a semiconductor chip, a conductive member for supporting the semiconductor chip, a joint...
2018/0286844 COOLING SYSTEM FOR HIGH POWER APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH EMBEDDED HIGH BANDWIDTH MEMORY
The subject disclosure relates to an integrated circuit package having an application specific integrated circuit, a high bandwidth memory, a first heat sink...
2018/0286843 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
A display apparatus includes: a display substrate; a light-emitting diode ("LED") disposed on the display substrate and which emits light; a passivation layer...
2018/0286842 LIGHT EMITTING DEVICE PACKAGE
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom,...
2018/0286841 Variable Resistance LED Device and Method
A LED lighting device is disclosed having a variable resistance device. The LED lighting device has a circuit. The circuit has a first circuit segment, a...
2018/0286840 THREE-DIMENSIONAL SMALL FORM FACTOR SYSTEM IN PACKAGE ARCHITECTURE
Embodiments are generally directed to three-dimensional small form factor system in package architecture. An embodiment of an apparatus includes a first...
2018/0286839 Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding...
2018/0286838 APPARATUS FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICE DIE
An apparatus for performing a direct transfer of a die. The apparatus includes a first frame to hold the first substrate and a second frame to hold the second...
2018/0286837 Chip On Board LED Device and Method
A LED device is disclosed. The device has a LED area, a boundary element surrounding the LED area, a plurality of chip scale package LEDs in the LED area, a...
2018/0286836 Sacrificial Alignment Ring And Self-Soldering Vias For Wafer Bonding
A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first...
2018/0286835 SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME
There may be provided a method of manufacturing a semiconductor package. The method may include forming a plurality of stack structures on a wafer to be...
2018/0286834 SYSTEM ON PACKAGE ARCHITECTURE INCLUDING STRUCTURES ON DIE BACK SIDE
Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising...
2018/0286833 Microelectronics Package Providing Increased Memory Component Density
Examples herein include a solid state drive microelectronics package assembly including a substrate and a plurality of microelectronic components coupled to...
2018/0286832 DECOUPLING SYSTEMS AND METHODS FOR SAME
A decoupling system includes a deflection plate configured for coupling across a low pressure orifice of a low pressure chamber. The deflection plate includes...
2018/0286831 METHOD FOR PRODUCING A SUBSTRATE ARRANGEMENT, SUBSTRATE ARRANGEMENT, AND METHOD FOR CONNECTING A SUBSTRATE...
One aspect relates to a method for manufacturing a substrate assembly for attachment to an electronic component A substrate is provided with a first side and...
2018/0286830 BUMP-ON-TRACE INTERCONNECT
Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump...
2018/0286829 RESIN COMPOSITION, BONDED BODY AND SEMICONDUCTOR DEVICE
A resin composition is provided, including a binder resin, and silver-coated particles in which a functional group is introduced to a surface. A ratio (a/b) of...
2018/0286828 MONOLITHIC DECOUPLING CAPACITOR BETWEEN SOLDER BUMPS
An integrated circuit includes pads formed on a back end of the line surface, and decoupling capacitor stacks monolithically formed about the pads. Solder...
2018/0286827 RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3)...
2018/0286826 METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION
Methods and apparatus are described for enabling copper-to-copper (Cu--Cu) bonding at reduced temperatures (e.g., at most 200.degree. C.) by significantly...
2018/0286825 MONOLITHIC DECOUPLING CAPACITOR BETWEEN SOLDER BUMPS
An integrated circuit includes pads formed on a back end of the line surface, and decoupling capacitor stacks monolithically formed about the pads. Solder...
2018/0286824 PACKAGE STRUCTURE AND METHOD OF FORMING PACKAGE STRUCTURE
A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second...
2018/0286823 PACKAGE STRUCTURE AND METHOD OF FORMING PACKAGE STRUCTURE
A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the...
2018/0286822 SUBSTRATE HAVING EMBEDDED ELECTRONIC COMPONENT
Disclosed are substrates having an electronic component, including a frame having a through hole, the electronic component disposed in the through hole, a...
2018/0286821 Integrated Circuit Capable of Operating at Very High Voltage and Method of Fabricating Same
An integrated circuit (IC) fabricated on a Silicon-On-Insulator (SOI) wafer, having a plurality of impedance elements cascoded in series, each impedance...
2018/0286820 Processing Techniques for Silicon-Based Transient Devices
Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor...
2018/0286819 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a...
2018/0286818 WAFER LEVEL PACKAGES, SEMICONDUCTOR DEVICE UNITS, AND METHODS OF FABRICATING THE SAME
A wafer level package and or a semiconductor device unit may be provided. The wafer level package may include semiconductor chips disposed on an ...
2018/0286817 METHOD OF MANUFACTURING ELECTRONIC COMPONENT MODULE
Forming a groove in a dicing region so as to expose a conductive pattern material on a side surface, closer to a first side of each of mounting regions, of a...
2018/0286816 ELECTRONIC COMPONENT MODULE
To provide an electronic component module capable of forming a shielding film in a state of an assembly substrate and enhancing productivity. An electronic...
2018/0286815 SHIELDING SOLUTIONS FOR DIRECT CHIP ATTACH CONNECTIVITY MODULE PACKAGE STRUCTURES HAVING SHIELDING STRUCTURES...
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a shielding structure...
2018/0286814 SEMICONDUCTOR POWER DEVICE AND A METHOD OF ASSEMBLING A SEMICONDUCTOR POWER DEVICE
Some embodiments are directed to a semiconductor power device and a method of assembling such a device is provided. The semiconductor power device includes a...
2018/0286813 ELECTRONIC COMPONENT MODULE AND METHOD OF MANUFACTURING THE SAME
A electronic device module includes a first substrate; electronic devices mounted on the first substrate; a second substrate coupled to a lower surface of the...
2018/0286812 Die Interconnect Substrates, a Semiconductor Device and a Method for Forming a Die Interconnect Substrate
Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the...
2018/0286811 Semiconductor Device and Method
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating...
2018/0286810 SEMICONDUCTOR DEVICE
A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate...
2018/0286809 MEMORY STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The...
2018/0286808 SEMICONDUCTOR DEVICE HAVING CONTACTS WITH VARYING WIDTHS
A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a...
2018/0286807 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a fuse element arranged on an interlayer insulating film formed on a semiconductor substrate. The fuse element is...
2018/0286806 SEMICONDUCTOR DEVICE HAVING MULTILAYER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes forming a stacked structure including at least one interconnection pattern layer and at least one...
2018/0286805 INTERFACE STRUCTURES AND METHODS FOR FORMING SAME
A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first...
2018/0286804 INTERCONNECTS FOR SEMICONDUCTOR PACKAGES
Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect...
2018/0286803 NON-PLANAR METAL-INSULATOR-METAL CAPACITOR FORMATION
A method for forming a semiconductor structure having a non-planar MIM capacitor is provided. The method includes forming a first dielectric layer on a base...
2018/0286802 STRUCTURE AND METHOD FOR IMPROVING HIGH VOLTAGE BREAKDOWN RELIABILITY OF A MICROELECTRONIC DEVICE
A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an...
2018/0286801 TRANSISTOR STRUCTURES
The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure...
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