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Patent # Description
2018/0301451 VERTICAL FET WITH REDUCED PARASITIC CAPACITANCE
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a...
2018/0301450 Two Dimension Material Fin Sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin...
2018/0301449 Two Dimension Material Fin Sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin...
2018/0301448 Two Dimension Material Fin Sidewall
A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin...
2018/0301447 METAL-OXIDE SEMICONDUCTOR (MOS) STANDARD CELLS EMPLOYING ELECTRICALLY COUPLED SOURCE REGIONS AND SUPPLY RAILS...
Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between...
2018/0301446 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first...
2018/0301445 Embedded PMOS-Trigger Silicon Controlled Rectifier (SCR) with Suppression Rings for Electro-Static-Discharge...
An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure...
2018/0301444 CHIP MODULE WITH SPATIALLY LIMITED THERMALLY CONDUCTIVE MOUNTING BODY
A module is disclosed. In one example, the module includes a carrier, an at least partially thermally conductive and electrically insulating body mounted on...
2018/0301443 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first...
2018/0301442 LIGHT EMITTING DIODE DISPLAY AND MANUFACTURE METHOD THEREOF
The present invention provides a light emitting diode display and a manufacture method thereof. The manufacture method of the light emitting diode forms the...
2018/0301441 LIGHT EMITTING DIODE DISPLAY AND MANUFACTURE METHOD THEREOF
The present invention provides a light emitting diode display and a manufacture method thereof. The manufacture method of the light emitting diode display...
2018/0301440 VERTICAL LIGHT EMITTING DIODE WITH MAGNETIC BACK CONTACT
A structure containing a vertical light emitting diode (LED) is provided. The vertical LED is present in an opening located in a display substrate, and the...
2018/0301439 Substrate with Array of LEDs for Backlighting a Display Device
A circuit component for a display includes a substrate and a circuit trace having a predetermined pattern disposed on a surface of the substrate. A plurality...
2018/0301438 LED SURFACE-MOUNT DEVICE AND LED DISPLAY INCORPORATING SUCH DEVICE
Surface-mount devices comprising a casing having opposed main surfaces, side surfaces, and end surfaces. A lead frame partially encased by the casing...
2018/0301437 LIGHT-EMITTING MODULE
Disclosed is a light-emitting module including: a first insulation film having light transmissive property; a conductor layer provided on the first insulation...
2018/0301436 Multiple bond via arrays of different wire heights on a same substrate
Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires ("first wires") extend from a surface of the...
2018/0301435 SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP
In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded...
2018/0301434 PACKAGING METHOD AND PACKAGE STRUCTURE FOR IMAGE SENSING CHIP
A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second...
2018/0301433 EMISSIVE LED DISPLAY DEVICE MANUFACTURING METHOD
A method of manufacturing an emissive LED display device, including the steps of forming a plurality of chips, each including at least one LED and, on a...
2018/0301432 Anisotropic Electrically Conductive Film and Connection Structure
An anisotropic electrically conductive film includes electrically conductive particles disposed in an electrically insulating adhesive layer. The particles are...
2018/0301431 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate...
2018/0301430 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least...
2018/0301429 Semiconductor Device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper...
2018/0301428 MILLIMETER WAVE INTEGRATED CIRCUIT WITH BALL GRID ARRAY PACKAGE INCLUDING TRANSMIT AND RECEIVE CHANNELS
A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond...
2018/0301427 SYSTEMS AND METHODS FOR INHIBITING BACKEND ACCESS TO INTEGRATED CIRCUITS BY INTEGRATING PHOTON AND ELECTRON...
Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons,...
2018/0301426 Protecting Analog Circuits with Parameter Biasing Obfuscation
A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor...
2018/0301425 BACKSIDE SUBSTRATE OPENINGS IN TRANSISTOR DEVICES
A method for fabricating a transistor device involves providing a substrate, forming an oxide layer over at least a portion of the substrate, forming a...
2018/0301424 Package Structure
A package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the...
2018/0301423 CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement...
2018/0301422 SEMICONDUCTOR DEVICE
A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main...
2018/0301421 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a...
2018/0301420 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the...
2018/0301419 POROUS SILICON DICING
A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The...
2018/0301418 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure...
2018/0301417 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate...
2018/0301416 COPPER ETCHING INTEGRATION SCHEME
The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a...
2018/0301414 SEMICONDUCTOR DEVICE WITH MULTI-LAYER METALLIZATION
One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions...
2018/0301413 PRE-SPACER SELF-ALIGNED CUT FORMATION
Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is...
2018/0301412 Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Extending Conductor Laterally...
A method includes forming insulative material along the opposing sides of a conductive via and a conductive line in a vertical cross-section comprising forming...
2018/0301411 FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A fuse of a semiconductor device may include: fuse link suitable for extending in a first direction and connecting first and second electrodes; a dummy strip...
2018/0301410 Methods Of Forming A Semiconductor Device Comprising First And Second Nitride Layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
2018/0301409 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure...
2018/0301408 FORMING CONDUCTIVE PLUGS FOR MEMORY DEVICE
Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations...
2018/0301407 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH ISOLATED DUMMY PATTERN
A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and...
2018/0301406 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package includes a first semiconductor chip positioned above a first substrate. A second substrate is positioned above the first substrate. The...
2018/0301405 CONDUCTIVE BASE EMBEDDED INTERCONNECT
Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect...
2018/0301404 INTEGRATION OF A PASSIVE COMPONENT IN AN INTEGRATED CIRCUIT PACKAGE
A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package...
2018/0301403 INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIRCUIT PACKAGE
A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the...
2018/0301402 INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIRCUIT PACKAGE
A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the...
2018/0301401 MULTI-LEVEL LEAD FRAME STRUCTURES AND METHOD OF PROVIDING SAME
Techniques and mechanisms for providing connectivity to integrated circuitry using a lead frame. In an embodiment, the lead frame includes a conductor which...
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