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Patent # Description
2018/0315846 SCALABLE SGT STRUCTURE WITH IMPROVED FOM
A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial...
2018/0315845 Semiconductor Device and Transistor Cell Having a Diode Region
A semiconductor device includes a gate trench formed in a semiconductor body and having a first sidewall, a second sidewall opposite the first sidewall, and a...
2018/0315844 SEMICONDUCTOR DEVICE WITH III-NITRIDE CHANNEL REGION AND SILICON CARBIDE DRIFT REGION
Techniques are provided for forming a semiconductor device. In an aspect, a semiconductor device is provided that includes a silicon carbide (SiC) structure...
2018/0315843 ENHANCEMENT-MODE III-NITRIDE DEVICES
A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the...
2018/0315842 SILICON CARBIDE EPITAXIAL WAFER, SILICON CARBIDE INSULATED GATE BIPOLAR TRANSISTOR, AND METHOD OF MANUFACTURING...
The SiC-IGBT includes a p-type collector layer, an n.sup.--type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the...
2018/0315841 METHOD AND STRUCTURE FOR FORMING DIELECTRIC ISOLATED FINFET WITH IMPROVED SOURCE/DRAIN EPITAXY
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions...
2018/0315840 Deposition Selectivity Enhancement and Manufacturing Method Thereof
A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each...
2018/0315839 FINFET DEVICE WITH NON-RECESSED STI
A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate,...
2018/0315838 STACKED TRANSISTORS
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a...
2018/0315837 FINFET DEVICE WITH A REDUCED WIDTH
A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric...
2018/0315836 MANUFACTURING METHODS OF INORGANIC THIN FILM TRANSISTORS (TFTs) AND FLEXIBLE DISPLAY DEVICES
The present disclosure relates to a manufacturing method of inorganic thin film transistors (TFTs), including: forming a p-type semiconductor layer and a...
2018/0315835 FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a...
2018/0315834 FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a...
2018/0315833 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a gate structure, a plurality of nanowires, a sacrificial material, and an epitaxy structure. The gate structure...
2018/0315832 METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION
Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI...
2018/0315831 FINFET DEVICE AND METHOD OF FORMING SAME
A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first...
2018/0315830 FinFETs and Methods of Forming the Same
A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer...
2018/0315829 PREVENTION OF EXTENSION NARROWING IN NANOSHEET FIELD EFFECT TRANSISTORS
Methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of...
2018/0315828 PREVENTION OF EXTENSION NARROWING IN NANOSHEET FIELD EFFECT TRANSISTORS
Semiconductor devices and methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial...
2018/0315827 DIFFERENTIAL WORK FUNCTION BETWEEN GATE STACK METALS TO REDUCE PARASITIC CAPACITANCE
An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack...
2018/0315826 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second...
2018/0315825 VERTICAL FIN WITH A GATE STRUCTURE HAVING A MODIFIED GATE GEOMETRY
A method of forming a gate structure with a modified gate geometry, including, forming two gate spacers and a dummy gate fill on a channel, wherein the dummy...
2018/0315824 METHOD AND STRUCTURE FOR A LARGE-GRAIN HIGH-K DIELECTRIC
A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first...
2018/0315823 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, and a semiconductor layer. The...
2018/0315822 METHODS OF FORMING A GATE CONTACT STRUCTURE ABOVE AN ACTIVE REGION OF A TRANSISTOR
One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure,...
2018/0315821 METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR
One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate...
2018/0315820 HETEROJUNCTION DEVICES AND METHODS FOR FABRICATING THE SAME
Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material...
2018/0315819 SILICON CARBIDE SEMICONDUCTOR DEVICE
A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a...
2018/0315818 HIGH DOSE ANTIMONY IMPLANT THROUGH SCREEN LAYER FOR N-TYPE BURIED LAYER INTEGRATION
A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is...
2018/0315817 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The...
2018/0315816 ISOLATED SEMICONDUCTOR LAYER IN BULK WAFER BY LOCALIZED SILICON EPITAXIAL SEED FORMATION
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral...
2018/0315815 EPITAXIAL SUBSTRATE AND METHOD FOR FORMING THE SAME
An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an...
2018/0315814 BONDED SUBSTRATE FOR EPITAXIAL GROWTH AND METHOD OF FORMING THE SAME
A bonded substrate for epitaxial growth and a method for forming the same are disclosed. The method includes steps of providing a first substrate, which has a...
2018/0315813 SEMICONDUCTOR DEVICE
The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer...
2018/0315812 TERMINATION IMPLANT ENRICHMENT FOR SHIELDED GATE MOSFETS
In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor...
2018/0315811 CAPACITOR, SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE CAPACITOR AND THE SEMICONDUCTOR DEVICE
A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the...
2018/0315810 CHIP RESISTOR AND CHIP RESISTOR ASSEMBLY
A chip resistor includes a base substrate having a first surface and a second surface opposing each other, two side surfaces connecting the first surface and...
2018/0315809 DISPLAY APPARATUS
A display apparatus includes a substrate having a first area, a second area, and a bending area disposed therebetween. The substrate is bent at the bending...
2018/0315808 ORGANIC LIGHT EMITTING (OLED) DISPLAY PANELS, AND THE MANUFACTURING METHODS AND DISPLAY DEVICES THEREOF
The present disclosure relates to an OLED display panel and the manufacturing method and the display device thereof. The method includes: forming a plurality...
2018/0315807 PIXEL DEFINITION STRUCTURE, ORGANIC LIGHT-EMITTING DEVICE, ENCAPSULATION METHOD THEREOF, AND DISPLAY APPARATUS
A pixel definition structure, an organic light-emitting device and the encapsulation method thereof, and a display apparatus are provided, in the field of...
2018/0315805 ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE BACK PLATE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure provides an AMOLED back plate and a method for manufacturing the same. The manufacturing method includes: forming source and drain...
2018/0315804 METHOD FOR MANUFACTURING FLEXIBLE DISPLAY DEVICE AND FLEXIBLE DISPLAY DEVICE
The disclosure provides a method for manufacturing a flexible display device and a flexible display device. The manufacturing method comprises: providing a...
2018/0315803 DISPLAY SCREEN, DISPLAY DEVICE AND MOBILE TERMINAL
The present disclosure provides a display screen, including a display layer and a light shielding layer. The display layer includes an upper surface and a...
2018/0315802 DISPLAY DEVICE
According to one embodiment, a display device includes a display area, a first peripheral area, an organic insulating film. The display area is provided on a...
2018/0315801 DISPLAY DEVICE
A sub-pixel for a second color is disposed to be adjacent to a sub-pixel for a first color in a row direction. A sub-pixel for a third color is disposed to be...
2018/0315800 PIXEL STRUCTURE OF OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
A pixel structure of an organic light emitting diode (OLED) display panel and a manufacturing method thereof are disclosed. The pixel structure comprises a...
2018/0315799 ORGANIC LIGHT EMITTING DIODE DISPLAY MODULE AND CONTROL METHOD THEREOF
Provided are an organic light emitting diode display module, a control method for the organic light emitting diode display module, a display device and...
2018/0315798 PHOTODETECTOR
A photodetector includes: a semiconductor substrate including first and second impurity regions; a gate insulating layer located on a region of the...
2018/0315797 Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And...
A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising ...
2018/0315796 CROSS-POINT MEMORY ARRAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns...
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