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Patent # Description
2018/0315744 Power Semiconductor Devices and a Method for Forming a Power Semiconductor Device
A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further...
2018/0315743 SEMICONDUCTOR DEVICE
A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third...
2018/0315742 PROJECTION DISPLAY SYSTEM
A light-emitting diode (LED) projector includes an LED display panel and a projection lens arranged in front of LED display panel and configured to collect and...
2018/0315741 LIGHT-EMITTING DIODE (LED) DISPLAY ARRAY, MANUFACTURING METHOD THEREOF, AND WEARABLE DEVICE
A light-emitting diode (LED) display array, a manufacturing method thereof and a wearable device are provided. The LED display array comprises a first...
2018/0315740 SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME
A semiconductor device package includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second...
2018/0315739 DIE-BONDING SUBSTRATE, HIGH-DENSITY INTEGRATED COB WHITE LIGHT SOURCE AND METHOD FOR MANUFACTURING THE SAME
A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip...
2018/0315738 MICROELECTRONIC DIODE WITH OPTIMISED ACTIVE SURFACE
A diode including: first and second doped semi-conductor portions forming a p-n junction, a first part of the first portion being arranged between a second...
2018/0315737 INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
2018/0315736 SEMICONDUCTOR DEVICES INCLUDING A CONTROLLER AND METHODS OF FORMING SUCH DEVICES
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
2018/0315735 Embedded Organic Interposers for High Bandwidth
Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and...
2018/0315734 METHOD FOR MAKING AN ELECTRONIC COMPONENT PACKAGE
In making electronic component packages, a method includes forming a sacrificial material over a first temporary substrate, applying a second temporary...
2018/0315733 SEMICONDCUTOR PACKAGE
A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a...
2018/0315732 CAPILLARY TRANSPORT DEVICE, CAPILLARY MOUNTING DEVICE, CAPILLARY REPLACEMENT DEVICE, CAPILLARY TRANSPORT...
There is provided a capillary transport device capable of inserting, without manpower, a capillary into a mounting section of an ultrasonic horn. According to...
2018/0315731 INKJET PRINTABLE MASK APPARATUS AND METHOD FOR SOLDER ON DIE TECHNOLOGY
Described is an apparatus which comprises: a die with a first side; a plurality of metal bumps on the first side of the die; a plurality of solders disposed on...
2018/0315730 BACKSIDE METALIZATION WITH THROUGH-WAFER-VIA PROCESSING TO ALLOW USE OF HIGH Q BONDWIRE INDUCTANCES
A flip-chip integrated circuit die includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication...
2018/0315729 Thermal Bonding Sheet and Thermal Bonding Sheet with Dicing Tape
Provided is a thermal bonding sheet capable of preventing bonding irregularity by uniform thickness, and imparting the bonding reliability at high...
2018/0315728 STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE
Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the...
2018/0315727 SOLID-STATE IMAGING DEVICE
A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a...
2018/0315726 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions...
2018/0315725 PACKAGE STRUCTURE HAVING BUMP WITH PROTECTIVE ANTI-OXIDATION COATING
A package structure includes a semiconductor substrate: a pad disposed on the semiconductor substrate; a conductive layer disposed on the pad; a protection...
2018/0315724 METHOD FOR MAKING NANOSCALE DEVICES
A method of making nanoscale devices, the method including: depositing a metal film on a surface of a first substrate; annealing the metal film to form a...
2018/0315723 SEMICONDUCTOR DEVICE WITH POST PASSIVATION STRUCTURE AND FABRICATION METHOD THEREFOR
A method of fabricating a semiconductor device includes forming a first contact pad and a second contact pad over a first passivation layer, depositing a first...
2018/0315722 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A barrier layer BAL is formed so as to be in contact with an aluminum pad ALP. A titanium alloy layer including a titanium film and a titanium nitride film is...
2018/0315721 RADIO FREQUENCY CIRCUIT, WIRELESS COMMUNICATION DEVICE, AND METHOD OF MANUFACTURING RADIO FREQUENCY CIRCUIT
A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the...
2018/0315720 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate; an interconnect structure formed over the substrate and including a dielectric layer over the substrate, a...
2018/0315719 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device includes a carrier, an electronic component, a package body and an antenna. The carrier has a first surface, a second surface...
2018/0315718 SEMICONDUCTOR PACKAGES AND DEVICES
Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor...
2018/0315717 SHIELDED MODULE HAVING COMPRESSION OVERMOLD
A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging...
2018/0315716 METHODS AND MODULES RELATED TO SHIELDED LEAD FRAME PACKAGES
Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency...
2018/0315715 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package and a method for fabricating the same are provided. The method includes disposing an electronic component on a lower side of a first...
2018/0315714 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a circuit board, a chip, a housing, an antenna...
2018/0315713 Integrated Circuit Substrate and Method for Manufacturing the Same
An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality...
2018/0315712 EMBEDDED SUBSTRATE PACKAGE STRUCTURE
Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth...
2018/0315711 METAL GATE TRANSISTOR
A metal gate transistor is provided. The metal gate transistor includes a semiconductor substrate; a metal gate structure formed on the semiconductor...
2018/0315710 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
2018/0315709 STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND BEYOND
A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench...
2018/0315708 POWER RAIL AND MOL CONSTRUCTS FOR FDSOI
An electrical connection is provided between a source/drain of a planar transistor and a local interconnect or first metallization layer power rail, includes a...
2018/0315707 CRACK STOP WITH OVERLAPPING VIAS
A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a...
2018/0315706 Integrated Fan-Out Package with 3D Magnetic Core Inductor
Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are...
2018/0315705 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first...
2018/0315704 Semiconductor Structure
One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first...
2018/0315703 SURFACE NITRIDATION IN METAL INTERCONNECTS
A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first...
2018/0315702 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed...
2018/0315701 METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first...
2018/0315700 SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The...
2018/0315699 POST-GRIND DIE BACKSIDE POWER DELIVERY
Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a...
2018/0315698 PACKAGE SUBSTRATES
A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy...
2018/0315697 CIRCUITIZED SUBSTRATE WITH ELECTRONIC COMPONENTS MOUNTED ON TRANSVERSAL PORTION THEREOF
A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of...
2018/0315696 CIRCUITIZED SUBSTRATE WITH ELECTRONIC COMPONENTS MOUNTED ON TRANSVERSAL PORTION THEREOF
A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of...
2018/0315695 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board...
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