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Patent # Description
2018/0315694 TRACE/VIA HYBRID STRUCTURE WITH THERMALLY AND ELECTRICALLY CONDUCTIVE SUPPORT MATERIAL FOR INCREASED THERMAL...
A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method and forming a continuous seed metal...
2018/0315693 FLIP-CHIP DEVICE AND METHOD FOR PRODUCING A FLIP-CHIP DEVICE
In various embodiments, a flip-chip device is provided. The flip-chip device includes a chip having an electrically conductive chip contact, and a carrier...
2018/0315692 SUBSTRATE AND METHOD FOR FABRICATION THEREOF
A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace...
2018/0315691 SEMICONDUCTOR DEVICE
An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands...
2018/0315690 HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS
Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical...
2018/0315689 PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
2018/0315688 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
2018/0315687 BOARD AND METHOD OF MANUFACTURING BOARD
A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first...
2018/0315686 SEMICONDUCTOR DEVICE
A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively...
2018/0315685 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having...
2018/0315684 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a...
2018/0315683 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating circuit-substrate on which a semiconductor chip is mounted, a casing accommodating the insulating ...
2018/0315682 SYSTEMS AND METHODS FOR REINFORCED ADHESIVE BONDING USING TEXTURED SOLDER ELEMENTS
The present disclosure relates to a bonding system comprising a first substrate, a second substrate, an adhesive, in contact with a first contact surface and a...
2018/0315681 INTEGRATED CIRCUIT DIRECT COOLING SYSTEMS AND RELATED METHODS
Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer...
2018/0315680 LAMINATE AND METHOD OF MANUFACTURING LAMINATE
A laminate includes: an insulating substrate; an intermediate layer formed on a surface of the substrate and containing a metal or an alloy as a main...
2018/0315679 Circuit cooled on two-sides
The invention relates to a component (9) comprising a first ceramic substrate (1) with an upper side (1b) and a lower side (1a), wherein a metallization (2) is...
2018/0315678 PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a...
2018/0315677 EXTERNAL CONNECTION MECHANISM, SEMICONDUCTOR DEVICE, AND STACKED PACKAGE
A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a...
2018/0315676 SEMICONDUCTOR DEVICE
The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first...
2018/0315675 RESIN MOLDED BODY
A part of the sealed surface of the thermosetting resin member is a non-roughened surface that is not subjected to a roughening treatment. The other part of...
2018/0315674 PACKAGE PROCESS METHOD INCLUDING DISPOSING A DIE WITHIN A RECESS OF A ONE-PIECE MATERIAL
A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom...
2018/0315673 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip has an evaluation pattern that is included in a monitor pattern. This evaluation pattern is constituted by a first pattern and a second...
2018/0315672 SACRIFICIAL TEST PADS FOR INLINE TEST ACCESS
A chip assembly includes a first die pad on a first side of the chip assembly, the first side obscured and inaccessible during testing of the chip assembly....
2018/0315671 METHOD AND SYSTEM FOR MEASURING PATTERN PLACEMENT ERROR ON A WAFER
A method for measuring pattern placement error (PPE) on a wafer includes receiving a photomask pattern. One or more unit cell patterns are added to the...
2018/0315670 Guided Metrology Based on Wafer Topography
A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about...
2018/0315669 METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS
A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line...
2018/0315668 SILICON GERMANIUM AND SILICON FINS ON OXIDE FROM BULK WAFER
A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas...
2018/0315666 CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include ...
2018/0315665 METHOD FOR FABRICATING NFET AND PFET NANOWIRE DEVICES
Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method...
2018/0315664 FINFET DEVICE WITH DIFFERENT LINERS FOR PFET AND NFET AND METHOD OF FABRICATING THEREOF
A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure...
2018/0315663 DUAL CHANNEL SILICON/SILICON GERMANIUM COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PERFORMANCE WITH INTERFACE...
A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one...
2018/0315662 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second...
2018/0315661 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second...
2018/0315660 CONTACT RESISTANCE CONTROL IN EPITAXIAL STRUCTURES OF FINFET
A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and...
2018/0315659 INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE STRUCTURES AND METHODS ASSOCIATED THEREWITH
Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a...
2018/0315658 Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in...
2018/0315657 Substrate Manufacturing Method
A substrate manufacturing method includes: a first step of disposing a condenser for condensing a laser beam in a non-contact manner on a surface 20r of a...
2018/0315656 Wafer Level Dicing Method and Semiconductor Device
A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends...
2018/0315655 NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon...
2018/0315654 SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and...
2018/0315653 SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and...
2018/0315652 Metal Gates of Transistors Having Reduced Resistivity
A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric,...
2018/0315651 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Described herein is a technique capable of providing a semiconductor device having good characteristics. According to the technique described herein, there is...
2018/0315650 PROCESS INTEGRATION APPROACH OF SELECTIVE TUNGSTEN VIA FILL
Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an...
2018/0315649 METHOD OF FORMING TUNGSTEN FILM
A method of forming a tungsten film having low resistance is provided. The method includes forming a discontinuous film containing a metal on a substrate; and...
2018/0315648 ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and...
2018/0315647 Semiconductor Device and Method
A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier...
2018/0315646 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover...
2018/0315645 DOUBLE SPACER IMMERSION LITHOGRAPHY TRIPLE PATTERNING FLOW AND METHOD
A system and method for fabricating metal patterns are described. Multiple mandrels are formed on a first polysilicon layer which is on top of a first oxide...
2018/0315644 METHOD OF ELIMINATING FAULTS IN A SEMICONDUCTOR FILM COMPRISING THE FORMATION OF A HYDROGEN TRAPPING LAYER
The invention relates to a method of treating a thin film transferred from a donor substrate to a receiver substrate by fracture at the level of a zone of the...
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