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Patent # Description
2018/0331084 LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE
A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a...
2018/0331083 Power Converter Monolithically Integrating Transistors, Carrier, and Components
A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110)....
2018/0331082 CO-INTEGRATED III-N VOLTAGE REGULATOR AND RF POWER AMPLIFIER FOR ENVELOPE TRACKING SYSTEMS
Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor...
2018/0331081 INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FOR PLATFORM MINIATURIZATION
Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an...
2018/0331080 System-in-Package Devices and Methods for Forming System-in-Package Devices
A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a...
2018/0331079 WATERPROOF SEALED CIRCUIT APPARATUS AND METHOD OF MAKING THE SAME
A waterproof sealed circuit apparatus includes a circuit substrate having a first side opposite a second side. The first side includes a circuit trace. A...
2018/0331078 TUNABLE INTEGRATED OPTICS LED COMPONENTS AND METHODS
Light emitting diode (LED) devices and methods. An example apparatus can include a substrate, one or more LEDs, light-transmissive encapsulation material, and...
2018/0331077 POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR CORE MODULE
It is an object to provide a pressure-contact power semiconductor device and a power semiconductor core module which are capable of properly reducing their...
2018/0331076 SEMICONDUCTOR PACKAGES
A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second...
2018/0331075 SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and...
2018/0331074 Microelectronic Package Having Stub Minimization Using Symmetrically-Positioned Duplicate Sets of Terminals for...
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face...
2018/0331073 3D SEMICONDUCTOR DEVICE AND STRUCTURE
A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer...
2018/0331072 Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least...
2018/0331071 STACKED SEMICONDUCTOR PACKAGES, METHODS OF FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME
An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first...
2018/0331070 PACKAGE STACKING USING CHIP TO WAFER BONDING
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or...
2018/0331069 Package Structure and Method of Forming the Same
An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure...
2018/0331068 ELECTRONIC COMPONENT PACKAGE
An electronic component package according to an embodiment of the present disclosure includes a first substrate, a sealing member, a second substrate, and...
2018/0331067 Universal Surface-Mount Semiconductor Package
A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly...
2018/0331066 Processed stacked dies
Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die...
2018/0331065 ELECTRONIC SANDWICH STRUCTURE WITH TWO PARTS JOINED TOGETHER BY MEANS OF A SINTERING LAYER
A description is given of an electronic sandwich structure which has at least a first and a second part to be joined, which are sintered together by means of a...
2018/0331064 ELECTRICAL INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to...
2018/0331063 METHOD FOR JOINING ELECTRONIC PART USING A JOINING SILVER SHEET
A method for joining an electronic part, comprising: inserting a joining silver sheet between an electronic part and a substrate, to which the electronic part...
2018/0331062 ELECTRICAL COMPONENT WITH THIN SOLDER RESIST LAYER AND METHOD FOR THE PRODUCTION THEREOF
An electrical device and a method for the manufacture of an electrical device are specified. The device has a carrier with an upper side and a metallized...
2018/0331061 INTEGRATED DEVICE COMPRISING BUMP ON EXPOSED REDISTRIBUTION INTERCONNECT
A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer...
2018/0331060 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DETECTOR, METHODS FOR MANUFACTURING SAME, AND SEMICONDUCTOR CHIP OR...
In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel...
2018/0331059 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding...
2018/0331058 THROUGH-SUBSTRATE-VIAS WITH SELF-ALIGNED SOLDER BUMPS
A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder...
2018/0331057 THROUGH-SUBSTRATE-VIAS WITH SELF-ALIGNED SOLDER BUMPS
A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder...
2018/0331056 MIXED UBM AND MIXED PITCH ON A SINGLE DIE
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
2018/0331055 Semiconductor Package System and Method
A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die...
2018/0331054 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing...
2018/0331053 Electrical device and a method for forming an electrical device
An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure...
2018/0331052 TERAHERTZ DETECTOR COMPRISED OF P-N JUNCTION DIODE
A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the...
2018/0331051 MICROELECTRONIC DEVICES DESIGNED WITH HIGH FREQUENCY COMMUNICATION DEVICES INCLUDING COMPOUND SEMICONDUCTOR...
Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first...
2018/0331050 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
The disclosure relates to a semiconductor package device. The semiconductor package device includes a substrate having a first surface and a second surface...
2018/0331049 CHIP ON FILM PACKAGE
A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a first conductive film. The base film includes a...
2018/0331048 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure includes disposing a plurality of devices on a carrier; immersing the plurality of devices into a molding...
2018/0331047 REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS
Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer...
2018/0331046 SEMICONDUCTOR DEVICES WITH ALIGNMENT KEYS
A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern,...
2018/0331045 VARIABLE RESISTANCE VIAS AND RELATED METHODS
Implementations of a via for a semiconductor devices may include a first tungsten layer deposited conformally within the via, and may be recessed within the...
2018/0331044 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure...
2018/0331043 RLINK-GROUND SHIELDING ATTACHMENT STRUCTURES AND SHADOW VOIDING FOR DATA SIGNAL CONTACTS OF PACKAGE DEVICES;...
A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical...
2018/0331042 SIZE AND EFFICIENCY OF DIES
An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic...
2018/0331041 SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor package device, which includes a semiconductor die and a redistribution layer disposed over and electrically...
2018/0331040 DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain...
2018/0331039 SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The...
2018/0331038 3D Chip Sharing Data Bus
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least...
2018/0331037 Stacked IC Structure with System Level Wiring on Multiple Sides of the IC Die
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least...
2018/0331036 GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA...
A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground...
2018/0331035 MICROPROCESSOR PACKAGE WITH FIRST LEVEL DIE BUMP GROUND WEBBING STRUCTURE
A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts,...
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