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Patent # Description
2018/0331034 THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having...
2018/0331032 InFO Coil Structure and Methods of Manufacturing Same
A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material...
2018/0331031 Semiconductor Device with Slotted Backside Metal for Improving Q Factor
A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor...
2018/0331030 Ultra High Performance Interposer
An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in...
2018/0331029 Assemblies Which Include Wordlines Over Gate Electrodes
Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an...
2018/0331028 WAFER-SCALE POWER DELIVERY
A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has...
2018/0331027 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package and a method for fabricating the same are provide. An antenna substrate is stacked on a carrier structure stacking assembly. Since no...
2018/0331026 WIRING SUBSTRATE
A wiring substrate includes an insulation layer, a first wiring layer, and a second wiring layer. The first wiring layer is embedded in the insulation layer...
2018/0331025 SUPPORT TERMINAL INTEGRAL WITH DIE PAD IN SEMICONDUCTOR PACKAGE
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first...
2018/0331024 Electronic component
Electronic component having a first lead frame consisting of an electrically conductive material. The first lead frame carries a first semiconductor component....
2018/0331023 LEAD FRAME
A lead frame includes a frame part, a lead extending inward from the frame part and having a front surface and a back surface, and an external connection...
2018/0331022 DIE PACKAGE COMPONENT WITH JUMPER STRUCTURE AND MANUFACTURING METHOD THEREOF
A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead...
2018/0331021 DIE PACKAGE COMPONENT WITH JUMPER STRUCTURE AND MANUFACTURING METHOD THEREOF
A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead...
2018/0331020 PACKAGE WITH BACKSIDE PROTECTIVE LAYER DURING MOLDING TO PREVENT MOLD FLASHING FAILURE
A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The...
2018/0331019 SEMICONDUCTOR DEVICE
A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The...
2018/0331018 Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first...
2018/0331017 POWER SEMICONDUCTOR MODULE FOR A MOTOR VEHICLE AND MOTOR VEHICLE
A power semiconductor module for a motor vehicle. a plurality of unhoused power semiconductor chips are provided, which are arranged so that a liquid coolant...
2018/0331016 THREE-DIMENSIONAL HEAT-ABSORBING DEVICE
A three-dimensional heat absorbing device including: an airtight member defining an outer appearance of the three-dimensional heat absorbing device; a first...
2018/0331015 HEAT SPREADERS WITH STAGGERED FINS
An apparatus is provided which comprises: a first heat spreader surface, a second heat spreader surface, and a plurality of heat spreading fins on, and...
2018/0331014 HEAT DISSIPATION ASSEMBLY
A heat dissipating assembly including a layered stack of materials with a highly thermally conductive path for cooling a circuit, the stack including a...
2018/0331013 MOUNT STRUCTURE
A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount...
2018/0331012 CONTROL UNIT AND ELECTRIC POWER STEERING DEVICE
Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device....
2018/0331011 FLEXIBLE HEAT SPREADER LID
Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic...
2018/0331010 RFIC DEVICE AND METHOD OF FABRICATING SAME
A radio frequency integrated circuit (RFIC) device and a method for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer...
2018/0331009 RFIC DEVICE AND METHOD OF FABRICATING SAME
A radio frequency integrated circuit (RFIC) device and methods for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having...
2018/0331008 SEMICONDUCTOR DEVICE
The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside. The...
2018/0331007 A SENSOR SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A SENSOR SEMICONDUCTOR DEVICE
The sensor semiconductor device comprises a substrate (1) with a main surface (2), a sensor region (3) on or above the main surface, a coating layer (4) above...
2018/0331006 Method for Producing an Electrical Device Comprising a Covering Material
A method for producing an electrical device including an electrical component at least partially covered by a covering material having a cement material...
2018/0331005 SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
In order to improve reliability of a semiconductor device, in a semiconductor chip according to one embodiment, an uneven shape is formed on an exposed surface...
2018/0331004 PRE-MOLDED ACTIVE IC OF PASSIVE COMPONENTS TO MINIATURIZE SYSTEM IN PACKAGE
A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices...
2018/0331003 IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS
Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first...
2018/0331002 ELECTRONIC DEVICE
Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a...
2018/0331001 CIRCUIT AND METHOD FOR TESTING GATE LINES OF ARRAY SUBSTRATE
Related to is a gate on array. A circuit for testing a gate line of an array substrate includes: a test pad and a first switch unit which connects the test pad...
2018/0331000 Probe methodology for ultrafine pitch Interconnects
Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect...
2018/0330999 OVERLAY-CORRECTION METHOD AND A CONTROL SYSTEM USING THE SAME
A method of correcting an overlay includes: forming a first pattern on a first substrate; forming a second pattern on the first pattern; obtaining a first...
2018/0330998 PROCESS FOR FABRICATING SILICON-GERMANIUM STRIPS
A strip or portions of a strip of silicon-germanium is made by first producing a strip of silicon suspended above a substrate. At least a portion of the strip...
2018/0330997 METHOD OF FORMING VERTICAL TRANSISTOR DEVICE
The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of...
2018/0330996 FIELD EFFECT TRANSISTOR GATE STACK
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a...
2018/0330995 METHOD TO REDUCE FINFET SHORT CHANNEL GATE HEIGHT
Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD...
2018/0330994 PROCESS FOR VARIABLE FIN PITCH AND CRITICAL DIMENSION
A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays....
2018/0330993 3D Chip Sharing Power Circuit
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least...
2018/0330992 3D Chip Sharing Power Interconnect Layer
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least...
2018/0330991 Semiconductor Die Singulation and Structures Formed Thereby
An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the...
2018/0330990 METHOD OF PROCESSING WORKPIECE
A method of processing a workpiece with a cutting blade, the workpiece having a body of metal disposed in superposed relation to projected dicing lines,...
2018/0330989 Techniques for Creating a Local Interconnect Using a SOI Wafer
In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a...
2018/0330988 METHOD OF FORMING VERTICAL CHANNEL DEVICES
The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel...
2018/0330987 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal...
2018/0330986 METHOD OF PATTERNING TARGET LAYER
The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask...
2018/0330985 STAIRCASE ENCAPSULATION IN 3D NAND FABRICATION
Methods and apparatuses for depositing an encapsulation layer over a staircase structure during fabrication of a 3D NAND structure to prevent degradation of an...
2018/0330984 Packages with Through-Vias Having Tapered Ends
A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material,...
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