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Patent # Description
2018/0374874 Array Substrate, Display Panel and Display Device
An array substrate and a display device are provided. The array substrate includes a base substrate; a first active layer, located on the base substrate; a...
2018/0374873 Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout...
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode...
2018/0374872 Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid...
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode...
2018/0374871 Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid...
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode...
2018/0374870 Semiconductor Constructions
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
2018/0374869 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the...
2018/0374868 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a...
2018/0374867 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The...
2018/0374866 THREE-DIMENSIONAL MEMORY DEVICE HAVING DIRECT SOURCE CONTACT AND METAL OXIDE BLOCKING DIELECTRIC AND METHOD OF...
A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack...
2018/0374865 MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH STRESS COMPENSATION STRUCTURES AND METHOD OF MAKING THEREOF
An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently...
2018/0374864 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected...
2018/0374863 3D FLASH MEMORY CELLS WHICH DISCOURAGE CROSS-CELL ELECTRICAL TUNNELING
3-d flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs...
2018/0374862 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked...
2018/0374861 Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance
Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the...
2018/0374860 Methods of Forming NAND Memory Arrays
Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal...
2018/0374859 SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN
Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The...
2018/0374858 Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures
In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure and a third fin structure, which extend in a first...
2018/0374857 VERTICAL SRAM STRUCTURE
A vertical SRAM cell includes a first (1.sup.st) inverter having a 1.sup.st pull-up (PU) transistor and a 1.sup.st pull-down (PD) transistor. The 1.sup.st PU...
2018/0374856 SEMICONDUCTOR MEMORY DEVICE
The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first...
2018/0374855 Apparatuses Having Body Connection Lines Coupled with Access Devices
Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper...
2018/0374854 Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor
Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described...
2018/0374853 ON DIE VOLTAGE REGULATION WITH DISTRIBUTED SWITCHES
A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The...
2018/0374852 SEMICONDUCTOR DEVICE
Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an...
2018/0374851 SINGLE-DIFFUSION BREAK STRUCTURE FOR FIN-TYPE FIELD EFFECT TRANSISTORS
A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type...
2018/0374850 METHOD AND DEVICE FOR EMBEDDING FLASH MEMORY AND LOGIC INTEGRATION IN FINFET TECHNOLOGY
Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in...
2018/0374849 METHOD AND DEVICE FOR EMBEDDING FLASH MEMORY AND LOGIC INTEGRATION IN FINFET TECHNOLOGY
Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in...
2018/0374848 HETEROJUNCTION DIODE HAVING AN INCREASED NON-REPETITIVE SURGE CURRENT
A heterojunction diode is provided, including first and second semiconductor layers made of III-N material, the layers being superposed to form a...
2018/0374847 SEMICONDUCTOR APPARATUS
A method of manufacturing a semiconductor apparatus includes setting first and second areas on a semiconductor chip, forming a first transistor in the first...
2018/0374846 DUAL-SERIES VARACTOR EPI
A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor...
2018/0374845 METHOD FOR MANUFACTURING MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS
A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first...
2018/0374844 SEMICONDUCTOR DEVICE
A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall...
2018/0374843 MONOLITHICALLY INTEGRATED CHIP INCLUDING ACTIVE ELECTRICAL COMPONENTS AND PASSIVE ELECTRICAL COMPONENTS WITH...
An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first...
2018/0374842 SUBSTRATE ISOLATION FOR LOW-LOSS RADIO FREQUENCY (RF) CIRCUITS
Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions...
2018/0374841 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2018/0374840 SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF
The present technology relates to a semiconductor integrated circuit which operates with a low voltage and is capable of preventing destruction of a protection...
2018/0374839 NOVEL ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection...
2018/0374838 SEMICONDUCTOR STRUCTURE
A semiconductor structure comprises a transistor. The transistor comprises a semiconductor substrate, a first source/drain side doped region, a second...
2018/0374837 Patterning a Target Layer
A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming...
2018/0374836 Semiconductor Packages and Methods of Forming the Same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a...
2018/0374835 FLIP-CHIP LIKE INTEGRATED PASSIVE PREPACKAGE FOR SIP DEVICE
A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the...
2018/0374834 OPTICALLY TRANSPARENT PLATE WITH LIGHT EMITTING FUNCTION AND METHOD OF PRODUCING THE SAME
Provided is an optically transparent plate having a structure where an LED die is directly mounted on an optically transparent substrate, and light extraction...
2018/0374833 LOWER IC PACKAGE STRUCTURE FOR COUPLING WITH AN UPPER IC PACKAGE TO FORM A PACKAGE-ON-PACKAGE (PoP) ASSEMBLY...
Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes...
2018/0374832 CONDUCTIVE WIRE THROUGH-MOLD CONNECTION APPARATUS AND METHOD
A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48)...
2018/0374831 LIGHT EMITTING DEVICE REFLECTIVE BANK STRUCTURE
Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the...
2018/0374830 METHODS OF MAKING LIGHT-EMITTING ASSEMBLIES COMPRISING AN ARRAY OF LIGHT-EMITTING DIODES HAVING AN OPTIMIZED...
Light emitting assemblies comprise a plurality of Light Emitting Diode (LED) dies arranged and attached to common substrate to form an LED array having a...
2018/0374829 LIGHT EMITTING DIODE (LED) MASS-TRANSFER APPARATUS AND METHOD OF MANUFACTURE
Embodiments relate to mass-transfer methods useful for fabricating products containing Light Emitting Diode (LED) structures. LED arrays are transferred from a...
2018/0374827 SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME
A semiconductor assembly includes a face-to-face semiconductor sub-assembly electrically coupled to a circuit board by bonding wires. The face-to-face...
2018/0374826 SEMICONDUCTOR PACKAGE
A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (TSV); a first guard unit disposed...
2018/0374825 SEMICONDUCTOR PACKAGE
A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface...
2018/0374824 Semiconductor Packages with Thermal-Electrical-Mechanical Chips and Methods of Forming the Same
In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM...
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