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Patent # Description
2019/0007073 FRONT-END ARCHITECTURE THAT SUPPORTS UPLINK CARRIER AGGREGATION AND SIMULTANEOUS MIMO USING SWITCH COMBINING
Described herein are front-end architectures that use switch-combining in a MIMO module to provide uplink carrier aggregation and simultaneous MIMO operations...
2019/0007072 Wireless Terminal and Antenna Switching Control Method for Wireless Terminal
A wireless terminal and an antenna switching control method for a wireless terminal, where the wireless terminal includes a main antenna, a first antenna, and...
2019/0007071 ERROR CORRECTING ANALOG-TO-DIGITAL CONVERTERS
A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal,...
2019/0007070 SEQUENTIAL POWER TRANSITIONING OF MULTIPLE DATA DECODERS
Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a...
2019/0007069 BANDWIDTH EFFICIENT FEC SCHEME SUPPORTING UNEVEN LEVELS OF PROTECTION
In one embodiment, a device in a network splits each of a plurality of packets of two or more data streams into an equal number of fragments. The number of...
2019/0007068 EARLY-TERMINATION OF DECODING CONVOLUTIONAL CODES
A decoder having an input configured to receive a sequence of softbits presumed to correspond to a convolutionally-encoded codeword; and a decoding circuit...
2019/0007067 INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises:...
2019/0007066 INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises:...
2019/0007065 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2019/0007064 TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC...
2019/0007063 GENERATING HAMMING WEIGHTS FOR DATA
Embodiments herein provide for a controller that is operable to soft read a data bit a plurality of times, to generate a bit set for the data bit from the soft...
2019/0007062 EFFICIENT GENERALIZED TENSOR PRODUCT CODES ENCODING SCHEMES
A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction...
2019/0007061 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD
A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding...
2019/0007060 CORRECTION DATA
Correction data units for data packets of a data stream are generated. A correction data unit is based on a set of the data packets of the stream. The stream...
2019/0007059 COMPRESSION OF SEMI-STRUCTURED DATA
A method for compressing semi-structured data is discussed. The method includes accessing semi-structured data, the semi-structured data comprising a plurality...
2019/0007058 SSD COMPRESSION AWARE
Embodiments of the present invention include a compression system including one or more compressibility inputs; a compression predictor configured to predict...
2019/0007057 DELTA MODULATOR WITH VARIABLE FEEDBACK GAIN, ANALOG-TO-DIGITAL CONVERTER INCLUDING THE DELTA MODULATOR, AND...
A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first...
2019/0007056 FREQUENCY DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock...
2019/0007054 STROBE CENTERING APPARATUS AND METHOD
An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase...
2019/0007053 SERDES WITH ADAPTIVE CLOCK DATA RECOVERY
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream...
2019/0007052 APPARATUS AND METHODS FOR SYSTEM CLOCK COMPENSATION
Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated...
2019/0007051 Parametrically Activated Quantum Logic Gates
In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the...
2019/0007050 REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE
Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a...
2019/0007049 SELF-ADAPTIVE CHIP AND CONFIGURATION METHOD
Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in...
2019/0007048 INTEGRATED CIRCUIT AND PROCESS FOR FAMILY OF DIGITAL LOGIC FUNCTIONS
A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated...
2019/0007047 Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same
An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii)...
2019/0007046 GATE CONTROL FOR A TRISTATE OUTPUT BUFFER
A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first...
2019/0007045 SEMICONDUCTOR DEVICE
A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter...
2019/0007044 METHOD FOR MANAGING A CAPACITIVE KEYBOARD FITTED TO A MOTOR VEHICLE
A method for managing a capacitive keyboard fitted to a motor vehicle, the capacitive keyboard comprising a plurality of keys connected to an electronic...
2019/0007043 Circuit with Impedance Elements Connected to Sources and Drains of PMOSFET Headers
A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to...
2019/0007042 Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When...
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices...
2019/0007041 ELECTRICAL CIRCUIT ARRANGEMENT WITH AN ACTIVE DISCHARGE CIRCUIT
The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by...
2019/0007040 Drive Voltage Booster
This disclosure describes a gate driver with voltage boosting capabilities. In some embodiments, the gate driver may comprise a charge pump that includes...
2019/0007039 SEMICONDUCTOR DEVICE, POWER MODULE, AND CONTROL METHOD OF POWER CONVERSION DEVICE
The junction temperature of a field effect transistor is detected with a higher degree of accuracy than in the past. A semiconductor device controls multiple...
2019/0007038 NON-OSCILLATING COMPARATOR
A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A...
2019/0007037 COMPARATOR
A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock...
2019/0007036 Clock Duty Cycle Calibration and Frequency Multiplier Circuit
Provided is a clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier, comprising: a multiplexing module...
2019/0007035 DELAY CELL AND CIRCUIT INCLUDING THE SAME
A delay cell may include: a first inverter coupled to an input terminal; a second inverter coupled between the first inverter and an output terminal; an...
2019/0007034 CLOCK SIGNAL GENERATOR CIRCUIT
A clock signal generator circuit includes a CR oscillator part, which outputs a clock signal having a frequency corresponding to a time constant determined by...
2019/0007033 TUNNEL FIELD-EFFECT TRANSISTOR (TFET) BASED HIGH-DENSITY AND LOW-POWER SEQUENTIAL
Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type...
2019/0007032 BUFFER CIRCUIT AND DEVICE INCLUDING THE SAME
A buffer circuit may include: a current mirror circuit suitable for selectively forming a first current mirror corresponding to a first power source voltage,...
2019/0007031 SEMICONDUCTOR DEVICE WITH POWER GATING SCHEME
A semiconductor device includes: a power-gated logic circuit suitable for operating in response to a first power gating enable signal which is deactivated in a...
2019/0007030 COMPOSITE FILTER DEVICE, HIGH-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION DEVICE
A composite filter device includes an antenna common terminal, a first band pass filter having a first pass band, and a second band pass filter having a second...
2019/0007029 PIEZOELECTRIC THIN FILM RESONATOR, FILTER, AND MULTIPLEXER
A piezoelectric thin film resonator includes: a substrate; a lower electrode located on the substrate through an air gap; a piezoelectric film located so as to...
2019/0007028 ELLIPTICALLY-SHAPED RESONATOR MARKERS WITH ENHANCED FREQUENCY STABILITY AND GAIN
A magnetoelastic resonator device comprises a housing, at least one elliptically-shaped or substantially elliptically-shaped magnetoelastic element disposed...
2019/0007027 RESONATOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE
A resonator device includes first and second resonators and an integrated circuit. The integrated circuit includes first and second oscillation circuits that...
2019/0007026 GALLIUM NITRIDE STRUCTURE, PIEZOELECTRIC ELEMENT, METHOD OF MANUFACTURING PIEZOELECTRIC ELEMENT, AND RESONATOR...
A gallium nitride structure that includes: a substrate; a gallium nitride layer opposed to the substrate and containing gallium nitride as a main component...
2019/0007025 METHOD OF PRODUCING LITHIUM NIOBATE SINGLE CRYSTAL SUBSTRATE
To provide a method of producing a lithium niobate (LN) substrate which allows treatment conditions regarding a temperature, a time, and the like to be easily...
2019/0007024 SUBSTRATE FOR A TEMPERATURE-COMPENSATED SURFACE ACOUSTIC WAVE DEVICE OR VOLUME ACOUSTIC WAVE DEVICE
A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support...
2019/0007023 ACOUSTIC WAVE RESONATORS HAVING FRESNEL SURFACES
Acoustic wave resonators having Fresnel features are disclosed. An example integrated circuit package includes an acoustic wave resonator, the acoustic wave...
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