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Patent # Description
2019/0006414 Magnetic Memory Element with Multilayered Seed Structure
The present invention is directed to a magnetic structure, which includes a magnetic fixed layer structure formed on top of a seed layer structure. The seed...
2019/0006413 INTEGRATED VERTICAL TRANSISTORS AND LIGHT EMITTING DIODES
The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of...
2019/0006412 IMAGING ELEMENT, DRIVING METHOD OF IMAGING ELEMENT, AND ELECTRONIC DEVICE
The present technology relates to an imaging element, a driving method of an imaging element, and an electronic device capable of preventing deterioration in...
2019/0006411 SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
The present technology relates to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode and prevent Qs from...
2019/0006410 SOLID-STATE IMAGE SENSING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS
The present disclosure relates to a solid-state image sensing device, a manufacturing method, and an electronic apparatus, in which surface roughness on a...
2019/0006409 BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS
A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures....
2019/0006408 IMAGE SENSOR DEVICE WITH REFLECTIVE STRUCTURE AND METHOD FOR FORMING THE SAME
An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front...
2019/0006407 SOLID-STATE IMAGING APPARATUS AND ELECTRONIC DEVICE
The present technology relates to a solid-state imaging apparatus and an electronic device that are configured to enhance the accuracy in the detection of...
2019/0006406 IMAGING ELEMENT AND CAMERA SYSTEM
An imaging element includes a plurality of photoelectric conversion sections. The photoelectric conversion sections are arrayed on a substrate to receive light...
2019/0006405 IMAGE PICKUP APPARATUS, ENDOSCOPE AND IMAGE PICKUP APPARATUS MANUFACTURING METHOD
An image pickup apparatus includes: an image pickup device with a light receiving portion being formed on a light receiving face; cover glass bonded to the...
2019/0006404 PACKAGING STRUCTURE AND PACKAGING METHOD
A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a...
2019/0006403 IMAGING SENSOR, IMAGING SYSTEM, AND MOVING BODY
An imaging sensor according to an exemplary embodiment includes a first semiconductor substrate, a second semiconductor substrate, a plurality of pixels, each...
2019/0006402 PHOTODETECTION DEVICE AND IMAGING DEVICE
A photodetection device includes: a photoelectric converter generating charge; a first diffusion region having a first end connected to the photoelectric...
2019/0006401 CURVED IMAGE SENSOR
A curved image sensor includes: a supporting substrate; an image sensor chip formed over the supporting substrate and including a curved light incidence...
2019/0006400 IMAGE SENSING DEVICE AND IMAGE SENSING METHOD
An image sensing device and an image sensing method are provided. The image sensing device includes an image sensing array, multiple first signal converters,...
2019/0006399 PHOTODETECTOR
A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric...
2019/0006398 METHOD FOR MANUFACTURING ARRAY SUBSTRATE
A method for manufacturing an array substrate is provided. The method includes the following. A signal transmission line and a gate electrode are formed on an...
2019/0006397 SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored...
2019/0006396 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND...
A method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate, and a display device are provided. The...
2019/0006395 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY PANEL
The disclosure discloses an array substrate, a method for manufacturing the same, and a display panel, and the array substrate includes a gate, an active...
2019/0006394 Displays With Silicon and Semiconducting Oxide Thin-Film Transistors
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display...
2019/0006393 SEMICONDUCTOR DEVICE
A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided....
2019/0006392 HYBRID FINFET STRUCTURE
A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a...
2019/0006391 Integrated Circuit Structure and Method with Hybrid Orientation for FinFET
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second...
2019/0006390 ELECTROLUMINESCENCE DISPLAY DEVICE
An electroluminescence display device is disclosed, which may use a polysilicon thin film transistor and an oxide thin film transistor together by using a dual...
2019/0006389 Array substrate, method for manufacturing the same and display panel
An array substrate, a method for manufacturing the same and a display panel are provided. The array substrate comprises: a substrate; a bare chip fixed on the...
2019/0006388 METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS...
Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a...
2019/0006387 THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
2019/0006386 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening,...
2019/0006385 SEMICONDUCTOR DEVICES
A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a...
2019/0006384 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first...
2019/0006383 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a...
2019/0006382 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of...
2019/0006381 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING HYDROGEN DIFFUSION BARRIER LAYER FOR CMOS UNDER ARRAY ARCHITECTURE...
A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen...
2019/0006380 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A...
2019/0006379 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die...
2019/0006378 NONVOLATILE MEMORY STRUCTURE AND ARRAY
A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region...
2019/0006377 HIGHLY COMPACT FLOATING GATE ANALOG MEMORY
A method for forming a floating gate memory cell includes: forming an active region on a semiconductor substrate; forming a gate stack on the active region,...
2019/0006376 Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of...
A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor...
2019/0006375 SEMICONDUCTOR DEVICE
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a...
2019/0006374 FINFET SRAM HAVING DISCONTINUOUS PMOS FIN LINES
An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of...
2019/0006373 PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM
A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate...
2019/0006372 EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME
A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down...
2019/0006371 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to...
2019/0006370 PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM
A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate...
2019/0006369 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which...
2019/0006368 SEMICONDUCTOR STRUCTURE HAVING AIR GAP BETWEEN GATE ELECTRODE AND DISTAL END PORTION OF ACTIVE AREA
A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the...
2019/0006367 Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory...
2019/0006366 METAL-INSULATOR-METAL CAPACITOR ANALOG MEMORY UNIT CELL
A memory device including a plurality of memory unit cells arranged in a crossbar configuration for a neural network is provided. Each of the memory unit cells...
2019/0006365 Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays
Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines...
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