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Patent # Description
2019/0006364 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions...
2019/0006363 ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The...
2019/0006362 NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are...
2019/0006361 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method is presented. The manufacturing method includes providing a semiconductor structure, comprising: a substrate, a...
2019/0006360 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion...
2019/0006359 POLYSILICON STRUCTURE INCLUDING PROTECTIVE LAYER
A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the...
2019/0006358 Mixed P/N MOS Array Layout and Methods of Forming the Same
A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD)...
2019/0006357 Power Semiconductor Device Having Different Gate Crossings, and Method for Manufacturing Thereof
A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the...
2019/0006356 PACKAGE WITH EMBEDDED CAPACITORS
An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the...
2019/0006355 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a...
2019/0006354 Integrated Circuit Packages and Methods of Forming Same
An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a...
2019/0006353 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film...
2019/0006352 TRANSITION FREQUENCY MULTIPLIER SEMICONDUCTOR DEVICE
A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first...
2019/0006351 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one...
2019/0006350 PASSIVE DEVICE STRUCTURE AND METHODS OF MAKING THEREOF
Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric...
2019/0006349 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring...
2019/0006348 ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE
An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A...
2019/0006347 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of...
2019/0006346 Power Gating for Three Dimensional Integrated Circuits (3DIC)
A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active...
2019/0006345 METAL GATE STRUCTURE CUTTING PROCESS
Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate...
2019/0006344 An Embedded High Voltage LDMOS-SCR Device with a Strong Voltage Clamp and ESD Robustness
The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD...
2019/0006343 Photomask Design for Generating Plasmonic Effect
A method includes providing a photomask having a patterned absorption layer over a substrate. The photomask is irradiated with a beam having a mixture of...
2019/0006342 RIGID ADHESIVE PACKAGE-ON-PACKAGE SEMICONDUCTORS
Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package...
2019/0006340 I/O Layout Footprint For Multiple 1LM/2LM Configurations
An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower...
2019/0006339 THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE
An integrated fan-out wafer level package houses a semiconductor package having a first semiconductor die encapsulated by a dielectric compound. A plurality of...
2019/0006338 ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS
In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically...
2019/0006337 LIGHT EMITTING DEVICE
A light emitting device includes a package having a recess which includes a bottom surface having corners. The package includes a first electrode, a second...
2019/0006336 LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME
A method of manufacturing a light emitting device includes: providing a semiconductor stack including a first semiconductor layer and a second semiconductor...
2019/0006335 DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME
Disclosed herein are a display device with a reduced bezel area and a method for fabricating the same. A wiring electrode disposed on a substrate is...
2019/0006334 INTEGRATED PASSIVE DEVICES ON CHIP
Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package,...
2019/0006333 CAPACITORS EMBEDDED IN STIFFENERS FOR SMALL FORM-FACTOR AND METHODS OF ASSEMBLING SAME
A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die...
2019/0006332 Structure and Formation Method for Chip Package
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely...
2019/0006331 ELECTRONICS PACKAGE DEVICES WITH THROUGH-SUBSTRATE-VIAS HAVING PITCHES INDEPENDENT OF SUBSTRATE THICKNESS
An electronics package device having a through-substrate-via comprises a substrate having a cavity and at least one electronic component (e.g., stack of dies)...
2019/0006330 ILLUMINATION ASSEMBLY, METHOD OF MANUFACTURING THE ILLUMINATION ASSEMBLY, AND BACKLIGHT MODULE INCLUDING THE...
An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed...
2019/0006329 BACKPLANE LED INTEGRATION AND FUNCTIONALIZATION STRUCTURES
Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall...
2019/0006328 DISPLAY DEVICE
A display device is provided. The display device includes a first substrate, a first light-emitting element, a second substrate, a light conversion layer and a...
2019/0006327 LIGHT EMITTING DIODE APPARATUS AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a light emitting diode (LED) apparatus is provided. The method includes forming a plurality of color filters on a glass layer,...
2019/0006326 LED PACKAGE, LED MODULE AND METHOD FOR MANUFACTURING LED PACKAGE
Disclosed is an LED package, an LED module and a method for manufacturing the LED package. The LED package includes a lead frame comprising an insulating...
2019/0006325 SEMICONDUCTOR PACKAGE HAVING SPACER LAYER
Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions...
2019/0006324 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor...
2019/0006323 THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the...
2019/0006322 METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE
A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n)...
2019/0006321 SEMICONDUCTOR DIE ASSEMBLIES HAVING MOLDED UNDERFILL STRUCTURES AND RELATED TECHNOLOGY
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate...
2019/0006320 SEMICONDUCTOR DEVICE INCLUDING CONTROL SWITCHES TO REDUCE PIN CAPACITANCE
A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically...
2019/0006319 PACKAGE ON PACKAGE THERMAL TRANSFER SYSTEMS AND METHODS
Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package...
2019/0006318 MONOLITHIC SILICON BRIDGE STACK INCLUDING A HYBRID BASEBAND DIE SUPPORTING PROCESSORS AND MEMORY
A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A...
2019/0006317 Package Structures and Methods of Forming
Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after...
2019/0006316 Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a...
2019/0006315 SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME
A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit...
2019/0006314 FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a...
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