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Patent # Description
2019/0006313 METHOD FOR PERMANENT BONDING OF WAFERS
A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps:...
2019/0006312 LEAD-FREE SOLDER JOINING OF ELECTRONIC STRUCTURES
A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders...
2019/0006311 Method for Producing Electronic Device With Multi-Layer Contact
A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having...
2019/0006310 MOUNTING COMPONENT, SEMICONDUCTOR DEVICE USING SAME, AND MANUFACTURING METHOD THEREOF
A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on...
2019/0006309 CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A method for forming a chip package structure is provided. The method includes forming a first dielectric layer over a carrier substrate. The first dielectric...
2019/0006308 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE
A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump....
2019/0006307 PACKAGE METHOD AND PACKAGE STRUCTURE OF FAN-OUT CHIP
A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without...
2019/0006306 SEMICONDUCTOR CHIP
A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second...
2019/0006305 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a semiconductor package structure is provided. The method includes the following steps. A first redistribution layer is formed on a...
2019/0006304 METAL PAD MODIFICATION
The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface...
2019/0006303 SEMICONDUCTOR DEVICE AND BUMP FORMATION PROCESS
A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region....
2019/0006302 PROCESS FOR FABRICATING A CIRCUIT SUBSTRATE
A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer,...
2019/0006301 3D Packaging Method for Semiconductor Components
The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is...
2019/0006300 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress...
2019/0006299 METHOD TO IMPROVE CMP SCRATCH RESISTANCE FOR NON PLANAR SURFACES
An electronic device is formed by providing a substrate having a recess at a top surface. A layer of an organic protective material is formed over the...
2019/0006298 PLATFORM WITH THERMALLY STABLE WIRELESS INTERCONNECTS
Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the...
2019/0006297 HIGH-POWER AMPLIFIER PACKAGE
Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry...
2019/0006296 METAL ON BOTH SIDES OF THE TRANSISTOR INTEGRATED WITH MAGNETIC INDUCTORS
An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each...
2019/0006295 PROTECTIVE FILM MATERIAL FOR LASER PROCESSING AND WAFER PROCESSING METHOD USING THE PROTECTIVE FILM MATERIAL
A protective film material for laser processing comprises a solution of a water-soluble adhesive and a water-soluble laser beam absorbent added to adjust...
2019/0006294 STIFFENER FOR A PACKAGE SUBSTRATE
Stiffener technology for electronic device packages is disclosed. A stiffener for a package substrate can include a top portion configured to be affixed to a...
2019/0006293 Semiconductor Package, and a Method for Forming a Semiconductor Package
A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the...
2019/0006292 Semiconductor Device and Method for Manufacturing the Semiconductor Device
A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a silicon carbide substrate and a protective...
2019/0006291 METHODS OF FORMING MULTI-CHIP PACKAGE STRUCTURES
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die...
2019/0006289 Semiconductor Device with Shielding Structure for Cross-Talk Reduction
A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over...
2019/0006288 SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE
A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding...
2019/0006287 MATCHED CERAMIC CAPACITOR STRUCTURES
Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and...
2019/0006286 GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE
An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first...
2019/0006285 METHOD FOR PRECISELY ALIGNING BACKSIDE PATTERN TO FRONTSIDE PATTERN OF A SEMICONDUCTOR WAFER
A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor...
2019/0006284 QUBIT NETWORK NON-VOLATILE IDENTIFICATION
A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators....
2019/0006283 Semiconductor Package and Method
In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated...
2019/0006282 MICROELECTRONIC DEVICES DESIGNED WITH MODULAR SUBSTRATES HAVING INTEGRATED FUSES
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic...
2019/0006281 CROSS-CONNECTED MULTI-CHIP MODULES COUPLED BY SILICON BENT-BRIDGE INTERCONNECTS AND METHODS OF ASSEMBLING SAME
A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the...
2019/0006280 INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor...
2019/0006279 COMPOUND LATERAL RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY
IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in...
2019/0006278 SEMICONDUCTOR DEVICE
Object is to provide a semiconductor device with fewer malfunctions. The semiconductor device has a semiconductor chip having a first-signal-output circuit...
2019/0006277 PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLING SAME
A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically...
2019/0006276 STRUCTURE AND METHOD FOR IMPROVING HIGH VOLTAGE BREAKDOWN RELIABILITY OF A MICROELECTRONIC DEVICE
A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic...
2019/0006275 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first...
2019/0006274 TRANSISTOR ASSEMBLIES
A transistor module assembly includes a longitudinally extending load bus bar, a longitudinally extending feed bus bar parallel to the load bus bar, and at...
2019/0006273 TRANSISTOR PACKAGES
In accordance with another aspect, a power switch assembly includes a transistor package including a die case, a source bus tab extending from a first side of...
2019/0006272 SEMICONDUCTOR DEVICE
In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not...
2019/0006271 MECHANICALLY FLEXIBLE INTERCONNECTS, METHODS OF MAKING THE SAME, AND METHODS OF USE
Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using...
2019/0006270 MOLDED INTELLIGENT POWER MODULE FOR MOTORS
An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a...
2019/0006269 Enhanced Thermal Transfer in a Semiconductor Structure
A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements...
2019/0006268 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions...
2019/0006267 SOLID TOP TERMINAL FOR DISCRETE POWER DEVICES
A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn...
2019/0006266 PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end...
2019/0006265 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE
This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding...
2019/0006264 EMBEDDED BRIDGE WITH THROUGH-SILICON VIAS
An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the...
2019/0006263 Heat Spreading Device and Method
In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of...
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