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Patent # Description
2019/0006262 DISSIPATING HEAT FROM AN ELECTRONIC DEVICE IN A PROTECTIVE HOUSING
An enclosed digital power amplifier has features for accommodating thermal cycling. The digital power amplifier includes an amplifier board and a controller...
2019/0006261 SILICON NITRIDE CIRCUIT BOARD AND ELECTRONIC COMPONENT MODULE USING THE SAME
The present invention provides a silicon nitride circuit board in which metal plates are attached on front and rear sides of a silicon nitride substrate having...
2019/0006260 Molded package with chip carrier comprising brazed electrically conductive layers
A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core...
2019/0006259 COOLING SOLUTION DESIGNS FOR MICROELECTRONIC PACKAGES
Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die...
2019/0006258 METHOD OF MANUFACTURING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE
Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a...
2019/0006257 SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME
A semiconductor package including at least one integrated circuit component, a glue material, an insulating encapsulation, and a redistribution circuit...
2019/0006256 Semiconductor Device and Method of Manufacture
In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is...
2019/0006255 POWER SEMICONDUCTOR DEVICE
At the time of clamping, excessive stress is applied to bonding parts between substrates and input/output terminals, which may cause the bonding parts to be...
2019/0006254 MICROELECTRONIC PACKAGE CONSTRUCTION ENABLED THROUGH CERAMIC INSULATOR STRENGTHENING AND DESIGN
A semiconductor packaging structure is disclosed. The semiconductor packaging structure includes a heat spreader, a set of at least two leads, and a ceramic...
2019/0006253 SEMICONDUCTOR CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREFOR
A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a...
2019/0006252 Semiconductor Package with Cavity
An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial...
2019/0006251 Package for a semiconductor die, method for making a die packaging bare die tape and method for semiconductor...
A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated...
2019/0006250 FABRICATION OF A SACRIFICIAL INTERPOSER TEST STRUCTURE
A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer,...
2019/0006249 OFFSET TEST PADS FOR WLCSP FINAL TEST
A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad;...
2019/0006248 METALIZATION REPAIR IN SEMICONDUCTOR WAFERS
Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor...
2019/0006247 METHOD OF FORMING PROTECTION LAYER IN FINFET DEVICE
A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin by an oxide layer and a...
2019/0006246 SEMICONDUCTOR DEVICE
This semiconductor device comprises: an n-type semiconductor substrate which is connected to an output terminal; a first p-type well which is formed in the...
2019/0006245 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of...
2019/0006244 SEMICONDUCTOR DEVICES, FINFET DEVICES, AND MANUFACTURING METHODS THEREOF
Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a...
2019/0006243 Structure and Formation Method of Semiconductor Device Structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
2019/0006242 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial...
2019/0006241 METHOD FOR DIRECT FORMING STRESSOR, SEMICONDUCTOR DEVICE HAVING STRESSOR, AND METHOD FOR FORMING THE SAME
A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between...
2019/0006240 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer...
2019/0006239 INTEGRATED CIRCUIT PACKAGE HAVING PIN-UP INTERCONNECT
An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an...
2019/0006238 MANUFACTURING PROCESS OF ELEMENT CHIP AND SUBSTRATE HEATING APPARATUS
Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing...
2019/0006237 PROTECTED CHIP-SCALE PACKAGE (CSP) PAD STRUCTURE
A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a...
2019/0006236 Self-Aligned Spacers and Method Forming Same
A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled...
2019/0006235 SEMICONDUCTOR DEVICE HAVING A LINER LAYER WITH A CONFIGURED PROFILE AND METHOD OF FABRICATING THEREOF
Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer...
2019/0006234 INTERCONNECTS WITH HYBRID METALLIZATION
Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the...
2019/0006233 Method of Forming Trenches
A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a...
2019/0006232 METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is...
2019/0006231 Interconnect Structure and Methods of Forming
An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein...
2019/0006230 INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA
Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top...
2019/0006229 PRODUCTION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP
A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first...
2019/0006228 FORMATION AND IN-SITU TREATMENT PROCESSES FOR GAP FILL LAYERS
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap...
2019/0006227 HIGH ASPECT RATIO GAP FILL
The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the...
2019/0006226 TUNGSTEN NITRIDE BARRIER LAYER DEPOSITION
Provided herein are methods of tungsten nitride (WN) deposition. Also provided are stacks for tungsten (W) contacts to silicon germanium (SiGe) layers and...
2019/0006225 ELECTROSTATIC CHUCK DESIGN FOR COOLING-GAS LIGHT-UP PREVENTION
A wafer support structure for use in a chamber used for semiconductor fabrication of wafers is provided. The wafer support structure includes a dielectric...
2019/0006224 SUBSTRATE PROCESSING METHOD
There is provided a processing method for a package substrate having a plurality of division lines formed on the front side. The processing method includes the...
2019/0006223 METHOD AND APPARATUS FOR WAFER LEVEL PACKAGING
Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a...
2019/0006222 3D SEMICONDUCTOR DEVICE AND STRUCTURE
A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory...
2019/0006221 METHOD FOR PRODUCING AN INTERFACE INTENDED TO ASSEMBLE TEMPORARILY A MICROELECTRONIC SUPPORT AND A MANIPULATION...
Method for producing an interface for assembling temporarily a microelectronic support and a handle, comprising at least: the formation of a first layer...
2019/0006220 Thermal Pad for Etch Rate Uniformity
Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a...
2019/0006219 METHOD OF PACKAGING CHIP AND CHIP PACKAGE STRUCTURE
A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress...
2019/0006218 SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY...
A substrate processing technique includes: a first heating device configured to heat a substrate to a first processing temperature; a first process chamber...
2019/0006217 CONVEYANCE SYSTEM
A conveyance system includes: a first track and a second track arranged parallel in a vertical direction such that device ports are positioned therebelow and...
2019/0006216 APPARATUS FOR TRANSPORTATION OF A SUBSTRATE CARRIER IN A VACUUM CHAMBER, SYSTEM FOR VACUUM PROCESSING OF A...
An apparatus for transportation of a substrate carrier in a vacuum chamber is provided. The apparatus includes a first track providing a first transportation...
2019/0006215 LIGHT IRRADIATION TYPE HEAT TREATMENT APPARATUS, AND HEAT TREATMENT METHOD
A semiconductor wafer transport mode of a heat treatment apparatus is switchable between two modes of a "high throughput mode" and a "low oxygen concentration...
2019/0006214 SYSTEM FOR A SEMICONDUCTOR FABRICATION FACILITY AND METHOD FOR OPERATING THE SAME
An apparatus for a semiconductor fabrication facility (FAB) is provided. In one embodiment, the apparatus includes a maintenance tool and a transporting tool...
2019/0006213 CHEMICAL SUPPLYING UNIT, SUBSTRATE TREATMENT APPARATUS, AND METHOD OF TREATING SUBSTRATE USING THE SUBSTRATE...
Provided is a substrate treatment apparatus including a housing, a supporting unit located inside the housing and supporting a substrate, a nozzle unit...
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