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Patent # Description
2019/0004995 High-Speed, Fixed-Function, Computer Accelerator
A hardware accelerator for computers combines a stand-alone, high-speed, fixed program dataflow functional element with a stream processor, the latter of which...
2019/0004994 PROCESSORS AND METHODS FOR PIPELINED RUNTIME SERVICES IN A SPATIAL ARRAY
Methods and apparatuses relating to pipelined runtime services in spatial arrays are described. In one embodiment, a processor includes processing elements; an...
2019/0004993 PROVIDING ACCESS FROM OUTSIDE A MULTICORE PROCESSOR SoC TO INDIVIDUALLY CONFIGURE VOLTAGES
Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an...
2019/0004992 CHIPSET WITH NEAR-DATA PROCESSING ENGINE
A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output...
2019/0004991 Method, Apparatus And System For Dynamic Control Of Clock Signaling On A Bus
In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an...
2019/0004990 TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT
Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a...
2019/0004989 External Resource Discovery and Coordination in a Data Center
Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled...
2019/0004988 QUEUE DEPTH MANAGEMENT FOR HOST SYSTEMS ACCESSING A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICE VIA...
Described herein are enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment. In...
2019/0004987 Programmable Adapter Between Slow Peripherals and Network On-Chip Interfaces
A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving...
2019/0004986 Scheduling Method, PCIe Switch and Electronic System Using the Same
The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is...
2019/0004985 FLASH-DRAM HYBRID MEMORY MODULE
A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the...
2019/0004984 DATA TRAINING METHOD OF STORAGE DEVICE
A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command...
2019/0004983 SEMICONDUCTOR DEVICE AND ACCESS CONTROL METHOD
Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller...
2019/0004982 BUFFER CIRCUIT AND DEVICE INCLUDING THE SAME
A circuit may include: a first buffer suitable for operating at a first supply voltage, buffering input data received through an input terminal, and outputting...
2019/0004981 CHIPSET WITH NEAR-DATA PROCESSING ENGINE
A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output...
2019/0004980 CYCLIC BUFFER POINTER FIXING
A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer...
2019/0004979 SYSTEMS AND METHODS FOR REDUCING WRITE LATENCY
A computer system having reduced write latency and methods for use in computer systems for reducing write latency are provided. Processing circuitry of the...
2019/0004978 SECURITY ROLE IDENTIFIER POOLS ALLOCATION
Various systems and methods for Security Attributes of Initiator (SAI) pools allocation are described herein. A system for security attribute pool allocation...
2019/0004977 RESETTING OPERATING STATE HOLDING ELEMENT
An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least...
2019/0004976 ACCESS OF VIRTUAL MACHINES TO STORAGE AREA NETWORKS
A method for managing access of virtual machines executed by a host computer system to storage area networks, the storage area networks connecting the host...
2019/0004975 STORAGE DRIVE AND METHOD OF EXECUTING A COMPARE COMMAND
A data storage device includes a memory and a controller coupled to the memory. The controller is configured to receive a compare command from a host, fetch or...
2019/0004974 TECHNIQUES FOR CRYPTO-AWARE CACHE PARTITIONING
Various embodiments are generally directed to techniques for crypto-aware cache partitioning, such as with a metadata cache for an integrity tree, for...
2019/0004972 MITIGATING ATTACKS ON KERNEL ADDRESS SPACE LAYOUT RANDOMIZATION
Various systems and methods for detecting and preventing side-channel attacks, including attacks aimed at discovering the location of KASLR-randomized...
2019/0004971 System and Method to Account for I/O Read Latency in Processor Caching Algorithms
A processor includes a cache memory and a cache controller. The cache controller fetches first data from a first location of an information handling system,...
2019/0004970 METHOD AND SYSTEM FOR LEVERAGING NON-UNIFORM MISS PENALITY IN CACHE REPLACEMENT POLICY TO IMPROVE PROCESSOR...
Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor...
2019/0004969 Caching System for Eventually Consistent Services
Systems, apparatuses, and methods may provide for an eventually-consistent distributed caching mechanism for database systems. As an example, the system may...
2019/0004968 CACHE MANAGEMENT METHOD, STORAGE SYSTEM AND COMPUTER PROGRAM PRODUCT
Embodiments of the present disclosure provide a cache management method, storage system and computer program product. The cache management method includes...
2019/0004967 Lookahead Priority Collection to Support Priority Elevation
A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system....
2019/0004966 SEMICONDUCTOR DEVICE
A semiconductor device includes associative memory, associated memory, a conversion register, a controller, and a synthetic data output unit. The associative...
2019/0004965 METHOD FOR SWITCHING ADDRESS SPACES VIA AN INTERMEDIATE ADDRESS SPACE
A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader...
2019/0004964 MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a...
2019/0004963 DUAL POINTER FOR MEMORY MAPPED INTERFACE COMMUNICATION
A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory...
2019/0004962 BRANCHLESS INSTRUCTION PAGING IN RECONFIGURABLE FABRIC
Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is...
2019/0004961 MEMORY TYPE WHICH IS CACHEABLE YET INACCESSIBLE BY SPECULATIVE INSTRUCTIONS
An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and...
2019/0004960 APPARATUS AND METHOD OF HANDLING CACHING OF PERSISTENT DATA
An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data...
2019/0004959 METHODS AND DEVICES FOR MANAGING CACHE
Embodiments of the present disclosure relate to methods and devices for managing cache. The method comprises in response to receiving a read request,...
2019/0004958 METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ SNAPSHOT AND IN PLACE WRITE UPDATE
Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in...
2019/0004957 LOW-OVERHEAD INDEX FOR A FLASH CACHE
Systems and methods for a low-overhead index for a cache. The index is used to access content or segments in the cache by storing at least an identifier and a...
2019/0004956 COMPUTER SYSTEM AND CACHE MANAGEMENT METHOD FOR COMPUTER SYSTEM
A cache state management mechanism manages the cache state of each of a first virtual computer and a second virtual computer, and if the cache state management...
2019/0004955 PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH MEMORY SYSTEM PERFORMANCE, POWER...
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of...
2019/0004954 APPLICATION AND PROCESSOR GUIDED MEMORY PREFETCHING
Devices and systems having memory-side adaptive prefetch decision-making, including associated methods, are disclosed and described. Adaptive information can...
2019/0004953 INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVICES AND SYSTEMS
Interleaved cache controllers with shared metadata are disclosed and described. A memory system may comprise a plurality of cache controllers and a metadata...
2019/0004952 COARSE TAG REPLACEMENT
An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to...
2019/0004951 POPULATING A SECOND CACHE WITH TRACKS FROM A FIRST CACHE WHEN TRANSFERRING MANAGEMENT OF THE TRACKS FROM A...
Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the...
2019/0004950 MEMORY NODE WITH CACHE FOR EMULATED SHARED MEMORY COMPUTERS
Data memory node (400) for ESM (Emulated Share Memory) architectures (100, 200), comprising a data memory module (402) containing data memory for storing input...
2019/0004949 MEMORY SYSTEM, MEMORY CONTROLLER FOR MEMORY SYSTEM, OPERATION METHOD OF MEMORY CONTROLLER, AND OPERATION METHOD...
A system includes: a nonvolatile memory; a memory controller configured to control the nonvolatile memory, the memory controller including a first buffer...
2019/0004948 SYSTEMS AND METHODS FOR PROGNOSTICATING LIKELIHOOD OF SUCCESSFUL SAVE OPERATION IN PERSISTENT MEMORY
In accordance with embodiments of the present disclosure, an information handling system may include a processor, a prognostic agent embodied in a program of...
2019/0004947 SELECTIVE TEMPORARY DATA STORAGE
One embodiment provides host device. The host device includes a host processor circuitry; a host memory circuitry, and a host storage logic to determine...
2019/0004946 METHOD AND DEVICE FOR CACHE MANAGEMENT
Embodiments of the present disclosure relate to a method and device for cache management. The method includes: receiving an I/O request associated with a...
2019/0004945 PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH TRANSACTIONAL AND REPLAY FEATURES
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of...
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