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Patent # Description
2019/0019784 SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE
According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a...
2019/0019783 METHOD OF PRODUCING AN OPTOELECTRONIC LIGHTING DEVICE AND OPTOELECTRONIC LIGHTING DEVICE
A method produces an optoelectronic lighting device. The device efficiently increases a decoupling of electromagnetic radiation from a volume emitter LED chip....
2019/0019782 LIGHT EMITTING ELEMENT
A light-emitting element provides a substrate; a plurality of light-emitting cells arranged on the substrate and spaced apart from each other; a connection...
2019/0019781 TRANSPARENT ACTIVE MATRIX DISPLAY COMPRISING EMITTING PIXELS WITH COLORED LIGHT-EMITTING DIODES
Displays are provided and including a transparent plate and a matrix array of pixels composed of light-emitted diodes arranged on the plate. In the display,...
2019/0019780 LIGHT EMITTING DEVICE PACKAGE
A light emitting device package includes: a plurality of light emitting chips configured to emit respective wavelength lights, each chip comprising electrodes...
2019/0019779 LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE USING THE SAME
A light emitting device package is provided. The light emitting device package includes three light emitting diode (LED) chips configured to emit light having...
2019/0019778 FACE-TO-FACE SEMICONDUCTOR ASSEMBLY HAVING SEMICONDUCTOR DEVICE IN DIELECTRIC RECESS
A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of...
2019/0019777 METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES
Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a...
2019/0019776 STRUCTURES AND METHODS FOR CAPACITIVE ISOLATION DEVICES
Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface...
2019/0019775 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF
A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first...
2019/0019774 METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES
A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each...
2019/0019773 SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different...
2019/0019772 METHOD FOR FORMING BUMP STRUCTURE
Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate...
2019/0019771 SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The...
2019/0019770 PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHES
An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric...
2019/0019769 METHOD OF PATTERN PLACEMENT CORRECTION
In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference...
2019/0019768 Three Terminal Solid State Plasma Monolithic Microwave Integrated Circuit
A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the...
2019/0019767 ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE
An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a...
2019/0019766 SEMICONDUCTOR DEVICE INCLUDING CIRCUIT HAVING SECURITY FUNCTION
A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality...
2019/0019765 Packaging Devices and Methods of Manufacture Thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device...
2019/0019764 SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING USING METAL LAYERS AND VIAS
A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon...
2019/0019763 SEMICONDUCTOR PACKAGE INCLUDING EMI SHIELDING STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate...
2019/0019762 SEMICONDUCTOR CHIP MODULE AND METHOD FOR ENHANCING VISUAL EFFECTS OF A PATTERN LAYER
A semiconductor chip module and a method for enhancing visual effects of a pattern layer, which relate to the field of semiconductor technology. The...
2019/0019761 SEMICONDUCTOR PACKAGES INCLUDING INDICATORS FOR EVALUATING A DISTANCE AND METHODS OF CALCULATING THE DISTANCE
A semiconductor package may include a package substrate to which a first semiconductor chip is attached, an encapsulant covering the first semiconductor chip,...
2019/0019760 MINI IDENTIFICATION MARK
A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central...
2019/0019759 SEMICONDUCTOR DEVICE
A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon...
2019/0019758 SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME
A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative...
2019/0019757 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first...
2019/0019756 SYSTEM ON INTEGRATED CHIPS AND METHODS OF FORMING THE SAME
A semiconductor device and methods of forming are provided. The method includes bonding a second die to a surface of a first die. The method includes...
2019/0019755 HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
2019/0019754 EMBEDDED VIALESS BRIDGES
Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are...
2019/0019753 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the...
2019/0019752 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2019/0019751 FUSE FABRICATION METHOD
The present invention discloses a polysilicon fuse fabrication method. The polysilicon fuse comprises a polysilicon fuse-link and two leading terminals, the...
2019/0019750 FUSE AND FABRICATION METHOD THEREOF
The present invention discloses a polysilicon fuse and fabrication method thereof. The polysilicon fuse comprises a polysilicon fuse-link and two leading...
2019/0019749 Integrated circuit structure, voltage-controlled oscillator and power amplifier
An integrated circuit structure includes a substrate, an integrated inductor, multiple components, multiple metal interconnections, a first shielding...
2019/0019748 PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN FOR BACK END OF LINE (BEOL) INTERCONNECT...
Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are...
2019/0019746 CLIP STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME
A clip structure and a semiconductor package using the same include different metals in multiple layers so as to selectively, easily and exactly fix...
2019/0019745 PACKAGE WITH BACKSIDE PROTECTIVE LAYER DURING MOLDING TO PREVENT MOLD FLASHING FAILURE
A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The...
2019/0019744 FINGERPRINT CHIP PACKAGE AND METHOD FOR PROCESSING SAME
A fingerprint chip package and method for processing same, relating to a field of biometric identification. The fingerprint chip package includes: a lead frame...
2019/0019743 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming...
2019/0019742 SEMICONDUCTOR DEVICE
A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess...
2019/0019741 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an...
2019/0019740 CERAMIC MODULE FOR POWER SEMICONDUCTOR INTEGRATED PACKAGING AND PREPARATION METHOD THEREOF
A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate...
2019/0019739 Thermal Conducting Sheet, Method for Manufacturing Thermal Conducting Sheet, Heat Dissipation Member, and...
Provided is a thermal conducting sheet, including: a binder resin; insulating-coated carbon fibers; and a thermal conducting filler other than the...
2019/0019738 HIGH FREQUENCY MODULE
A high frequency module improved in heat dissipation performance includes: a dielectric multilayer substrate including a ground layer and a high frequency...
2019/0019737 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD, IMAGING DEVICE, AND ELECTRONIC APPARATUS
The present technology relates to a semiconductor device and a manufacturing method, an imaging device, and an electronic apparatus that enable component...
2019/0019736 LASER-SEEDING FOR ELECTRO-CONDUCTIVE PLATING
A workpiece (100) having substrate, such as a glass substrate, can be etched by a laser or by other means to create recessed features (200, 202). A...
2019/0019735 TEST KEY AND METHOD FOR MONITORING SEMICONDUCTOR WAFER
A test key and a method for monitoring a semiconductor wafer are disclosed. The test key includes a first testing unit and a second testing unit. The first...
2019/0019734 OPTICAL EMISSION SPECTROSCOPIC TECHNIQUES FOR MONITORING ETCHING
Embodiments may include a method of etching. The method may also include flowing a gas mixture through a plasma discharge to form plasma effluents. The method...
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