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Patent # Description
2019/0019581 PLATFORM AND SYSTEM FOR DIGITAL PERSONALIZED MEDICINE
The methods and apparatus disclosed herein provide digital diagnostics and digital therapeutics to patients. The digital personalized medicine system uses...
2019/0019580 SPECIMEN ANALYSIS APPARATUS
The specimen analysis apparatus of the present invention comprises a measuring part; a display part; and a control part. The control part controls the...
2019/0019579 MEDICAL REPORTING APPARTUS
During a medical intervention such as an angiography, the X-ray examination equipment (such as that mounted on a C-arm) produces a very large number of imaging...
2019/0019578 SYSTEM FOR TRACKING PATIENT RECOVERY FOLLOWING AN ORTHOPEDIC PROCEDURE
An apparatus tracks patient recovery following an orthopedic procedure. A statistical computing engine implements a predictive model of the patient's...
2019/0019577 Subcutaneous Outpatient Management
A method of administering insulin includes receiving subcutaneous information for a patient at a computing device and executing a subcutaneous outpatient...
2019/0019576 PHARMACY FULFILLMENT AND VERIFICATION OF NON-STERILE COMPOUNDING
A method and apparatus for pharmacy fulfillment and verification of non-sterile compounding. A system includes an entry node, the entry node including at least...
2019/0019575 NASAL-RELATED CHARACTERIZATION ASSOCIATED WITH THE NOSE MICROBIOME
Embodiments of a method and/or system (e.g., for nasal-related characterization) can include determining a microorganism dataset associated with a set of...
2019/0019574 SYSTEM AND METHOD FOR CREATING AN ELECTRONIC CONSENT-BASED MEDICAL RECORD
An electronic consent-based medical record is created by: providing a processor(s) communicably coupled to an input/output interface, a memory and a data...
2019/0019573 PATIENT CARE SYSTEM
Patient care system comprising a medical device (1) for administering a medical treatment to a patient (15a) and a server system (6) configured to receive and...
2019/0019572 Means and Method for Improved Glycemic Control for Diabetic Patients
A glycemic control system includes a physician processor, remote processor, and a portable telephone having a data input mechanism, a display, and an internal...
2019/0019571 Method, System and Computer Program Product for Evaluation of Insulin Sensitivity, Insulin/Carbohydrate Ratio,...
A method, system and computer program product for evaluating or determining a user's insulin sensitivity (SI). An initial step or module may include acquiring...
2019/0019570 TECHNIQUES FOR CONDUCTING VIRTUAL CLINICAL TRIALS
Techniques and apparatus for generating, performing, and evaluating virtual clinical trials that include clinic modules to represent real-world operational...
2019/0019569 ROW REPAIR OF CORRECTED MEMORY ADDRESS
Addresses of memory cells that have errors corrected by error correction operations are evaluated to identify a failed row of memory. Post package repair is...
2019/0019568 FUSE-BLOWING SYSTEM AND METHOD FOR OPERATING THE SAME
The present disclosure provides a fuse-blowing system of a dynamic random access memory (DRAM). The fuse-blowing system includes a fuse device and a mapping...
2019/0019567 TEST LINE LETTER FOR EMBEDDED NON-VOLATILE MEMORY TECHNOLOGY
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having...
2019/0019566 Memory Devices Comprising Magnetic Tracks Individually Comprising A Plurality Of Magnetic Domains Having Domain...
A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an...
2019/0019565 Memory Device with a Fuse Protection Circuit
A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes...
2019/0019564 MULTIPLE (MULTI-) LEVEL CELL (MLC) NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS FOR PERFORMING MATRIX...
Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are...
2019/0019563 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory...
2019/0019562 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
Provided is a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory unit including a plurality...
2019/0019561 PAGE BUFFER, METHOD OF SENSING A MEMORY CELL USING THE SAME, AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME
A page buffer includes a first precharge circuit, a second precharge circuit, and a sense amplifying circuit. The first precharge circuit includes a first path...
2019/0019560 PRECHARGE CIRCUIT, AND MEMORY DEVICE AND SRAM GLOBAL COUNTER USING PRECHARGE CIRCUIT
A precharge circuit includes: a precharge time controller suitable for generating a precharge time control signal based on a threshold voltage of a transistor;...
2019/0019559 MEMORY DEVICE
A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control...
2019/0019558 MEMORY DEVICE AND OPERATING METHOD THEREOF
A memory device and an operating method thereof are provided. A memory device may include a plurality of source lines coupled to a memory block. The memory...
2019/0019557 SEQUENTIAL WRITE AND SEQUENTIAL WRITE VERIFY IN MEMORY DEVICE
Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory...
2019/0019556 METHODS AND APPARATUSES INCLUDING A STRING OF MEMORY CELLS HAVING A FIRST SELECT TRANSISTOR COUPLED TO A SECOND...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
2019/0019555 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes: a memory cell array including a...
2019/0019554 SEMICONDUCTOR DEVICES
A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a...
2019/0019553 APPARATUSES AND METHODS FOR MEMORY INCLUDING FERROELECTRIC MEMORY CELLS AND DIELECTRIC MEMORY CELLS
Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell...
2019/0019552 MULTIFUNCTIONAL MEMORY CELLS
The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge...
2019/0019551 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE
A nonvolatile memory device according to one embodiment includes a ferroelectric memory element and a resistive memory element. The ferroelectric memory...
2019/0019550 SRAM With Address Dependent Power Usage
A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near...
2019/0019549 ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors...
2019/0019548 ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors...
2019/0019547 ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors...
2019/0019546 3D Stacked High-Density Memory Cell Arrays and Methods of Manufacture
Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon...
2019/0019545 DUAL MODE MEMORY ARRAY SECURITY APPARATUS, SYSTEMS AND METHODS
Read-only ("RO") data consisting of a physically unclonable function ("PUF") pattern is written to a ferroelectric random-access memory ("FRAM") memory array....
2019/0019544 Memory Circuitry
Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor....
2019/0019543 APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A...
Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in...
2019/0019542 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The...
2019/0019541 DEVICE AND METHOD FOR DATA-WRITING
A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is...
2019/0019540 MEMORY DEVICE INCLUDING CURRENT GENERATOR PLATE
Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second...
2019/0019539 POWER SUPPLY AND POWER SUPPLYING METHOD THEREOF FOR DATA PROGRAMMING OPERATION
A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the...
2019/0019538 NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS EMPLOYING NVM MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS
Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein,...
2019/0019537 RETRACTABLE GUIDE FEATURES FOR DATA STORAGE DEVICE CARRIERS
Data storage device mounting systems to provide alignment and mounting of data storage devices are provided herein. A carrier is configured to couple to a data...
2019/0019536 MENU NAVIGATION MODE FOR MEDIA DISCS
Systems and methods are provided for reordering and/or bypassing certain informational content or menus that are conventionally presented prior to playback of...
2019/0019535 SYSTEMS AND METHODS OF THUMBNAIL GENERATION
A method includes receiving a plurality of images at an encoder device. The plurality of images is encoded by the encoder device to generate an output video...
2019/0019534 VIDEO CAMERA WITH CAPTURE MODES
Embodiments provide a video camera that can be configured to allow tagging of recorded video and/or capture of video segments or sequences of images in...
2019/0019533 METHODS FOR EFFICIENT ANNOTATION OF AUDIOVISUAL MEDIA
Disclosed herein are embodiments of the invention which allow for creating an audiovisual media project based on a primary audiovisual file and a secondary...
2019/0019532 Apparatus and Methods for Improving Video Quality From a Digital Video Signal Including Replicated Image Frames
A method includes receiving a first digital video signal having frames at a first frame rate. A respective frame of the first digital video signal is then...
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