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Patent # Description
2019/0018821 RECIPE GENERATION FOR IMPROVED MODELING
Systems and methods of generating recipes for modeling data sets are presented. Based on a corpus of a plurality of recipes for modeling data sets, an analysis...
2019/0018820 HIGH-SPEED INTER-PROCESSOR COMMUNICATIONS
A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having...
2019/0018819 METHOD AND APPARATUS FOR PUSHING ELECTRONIC BOOK
A method and device for pushing an electronic book. the method comprises: obtaining reading duration information sent by multiple terminals (210), the reading...
2019/0018818 ACCELERATED I3C STOP INITIATED BY A THIRD PARTY
Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a non-participating device to...
2019/0018817 HIGH SPEED COMMUNICATIONS NETWORK IN DENTAL EQUIPMENT
A system comprises a plurality of nodes connected in a peer-to-peer network via a communication interface. At least one node of the plurality of nodes...
2019/0018816 BUFFER CONTROLLER, MEMORY DEVICE, AND INTEGRATED CIRCUIT DEVICE
A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according...
2019/0018815 PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a synchronizer circuit...
2019/0018814 NETWORKED STORAGE SYSTEM WITH ACCESS TO ANY ATTACHED STORAGE DEVICE
In one embodiment, a networked system includes network interface ports to couple to a computer data network, PCIe devices, bridge devices coupled to network...
2019/0018813 POOLED MEMORY ADDRESS TRANSLATION
A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The...
2019/0018812 MASKING THE INFLUENCE OF UNSUPPORTED FIELDBUS COMMANDS
A control or test system for a field device includes: a communication unit for bidirectionally commmunicating with the field device via a fieldbus protocol; a...
2019/0018811 SYSTEMS FOR ENHANCING BOARDROOM TABLES TO INCLUDE USB TYPE-C POWER AND CONNECTIVITY FUNCTIONALITY
Boardroom table systems are provided that include a plurality of USB Type-C receptacles that can provide power and/or data transfer functionality to one or...
2019/0018810 A SYSTEM AND METHOD FOR PROGRAMMING DATA TRANSFER WITHIN A MICROCONTROLLER
A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a...
2019/0018809 MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first...
2019/0018808 MEMORY NODE CONTROLLER
A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data...
2019/0018807 ELECTRONIC DEVICE
An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits...
2019/0018806 TECHNIQUES FOR MANAGING ACCESS TO HARDWARE ACCELERATOR MEMORY
Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing...
2019/0018805 SYSTEM AND METHOD FOR FAST EXECUTION OF IN-CAPSULE COMMANDS
Systems and methods for fast execution of in-capsule commands are disclosed. NVM Express (NVMe) over fabrics is a standard in which a host device sends...
2019/0018804 CONFIGURABLE ORDERING CONTROLLER FOR COUPLING TRANSACTIONS
A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data...
2019/0018803 CONFIGURABLE ORDERING CONTROLLER FOR COUPLING TRANSACTIONS
A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first...
2019/0018802 USB2 HIGH SPEED CONNECTION FOR TESTING
In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection...
2019/0018801 SECURING FILES
Data security access and management may require a server dedicated to monitoring document access requests and enforcing rules and policies to limit access to...
2019/0018800 PROTECTING HOST MEMORY FROM ACCESS BY UNTRUSTED ACCELERATORS
A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a...
2019/0018799 Replacement Policies for a Hybrid Hierarchical Cache
A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same...
2019/0018798 COST-AWARE CACHE REPLACEMENT
Systems and methods relate to cost-aware cache management policies. In a cost-aware least recently used (LRU) replacement policy, temporal locality as well as...
2019/0018797 INFORMATION PROCESSING APPARATUS AND METHOD
An information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first...
2019/0018796 METHOD AND APPARATUS FOR AN EFFICIENT TLB LOOKUP
The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein...
2019/0018795 METHOD AND APPARATUS FOR AN EFFICIENT TLB LOOKUP
The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein...
2019/0018794 METHOD AND APPARATUS FOR FAST CONTEXT CLONING IN A DATA PROCESSING SYSTEM
A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a...
2019/0018793 SYSTEMS AND METHODS FOR TRANSFORMING LARGE DATA INTO A SMALLER REPRESENTATION AND FOR RE-TRANSFORMING THE...
A system comprises a processor with one or more cores; and memory including instructions to configure the processor to perform the method comprising receiving...
2019/0018792 CACHE RETURN ORDER OPTIMIZATION
Improving operation of a processing unit to access data within a cache system. A first fetch request and one or more subsequent fetch requests are accessed in...
2019/0018791 CACHE RETURN ORDER OPTIMIZATION
Improving operation of a processing unit to access data within a cache system. A first fetch request and one or more subsequent fetch requests are accessed in...
2019/0018790 METHOD AND APPARATUS FOR TWO-LAYER COPY-ON-WRITE
A system, apparatus and method are provided in which a range of virtual memory addresses and a copy of that range are mapped to the same first system address...
2019/0018789 MEMORY ADDRESS TRANSLATION
Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary...
2019/0018788 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of...
2019/0018787 FAST ADDRESS TRANSLATION FOR VIRTUAL MACHINES
A host machine uses a range-based address translation system rather than a conventional page-based system. This enables address translation to be performed...
2019/0018786 RANGE-BASED MEMORY SYSTEM
A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which...
2019/0018785 MEMORY SYSTEM FOR A DATA PROCESSING NETWORK
A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute...
2019/0018784 STORAGE CONTROL APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM STORING STORAGE CONTROL PROGRAM
A storing unit stores therein mapping management information indicating mappings between each of a plurality of divided regions created by dividing logical...
2019/0018783 Data access device and method applicable to processor
The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction...
2019/0018782 APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE
The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a...
2019/0018781 METHOD AND ARRANGEMENT FOR SAVING CACHE POWER
A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set...
2019/0018780 METHOD AND ARRANGEMENT FOR SAVING CACHE POWER
A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set...
2019/0018779 FILTERING OF REDUNDENTLY SCHEDULED WRITE PASSES
Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from...
2019/0018778 HIERARCHICAL NAND MEMORY DEVICE CAPABLE OF PERFORMING CONCURRENT AND PIPELINE OPERATIONS
A hierarchical NAND memory device includes: memory units each including memory groups; dynamic cache register (DCR) units each including DCR groups; switching...
2019/0018777 ADDRESS TRANSLATION CACHE PARTITIONING
An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets...
2019/0018776 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND METHOD OF CONTROLLING INFORMATION...
A first information-processing-apparatus includes a buffer to have entries to store a first request-data received and transmitted to a second...
2019/0018775 ACHIEVING HIGH BANDWIDTH ON ORDERED DIRECT MEMORY ACCESS WRITE STREAM INTO A PROCESSOR CACHE
Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated...
2019/0018774 COORDINATION OF CACHE AND MEMORY RESERVATION
A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least...
2019/0018773 SELECTIVE DOWNSTREAM CACHE PROCESSING FOR DATA ACCESS
A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will...
2019/0018772 SELECTIVE DOWNSTREAM CACHE PROCESSING FOR DATA ACCESS
A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will...
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