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Patent # Description
2019/0043869 METHOD FOR PRODUCING PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE
A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor...
2019/0043868 THREE-DIMENSIONAL (3D) MEMORY WITH CONTROL CIRCUITRY AND ARRAY IN SEPARATELY PROCESSED AND BONDED WAFERS
Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a...
2019/0043867 STATIC RANDOM ACCESS MEMORY AND FABRICATION METHODS THEREOF
A method for fabricating an SRAM includes forming a plurality of first fin structures, a plurality of second fin structures, and an isolation layer. Each first...
2019/0043866 METHOD FOR FORMING SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE
A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells...
2019/0043865 SEMICONDUCTOR STRUCTURE WITH CAPACITOR LANDING PAD AND METHOD OF MAKE THE SAME
The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor...
2019/0043864 DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME
A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes a substrate, an isolation...
2019/0043863 SEMICONDUCTOR DEVICE HAVING THYRISTOR AND METAL-OXIDE SEMICONDUCTOR TRANSISTOR
A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral...
2019/0043862 HETEROGENEOUSLY INTEGRATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom...
2019/0043861 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes...
2019/0043860 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower...
2019/0043859 POWER TRANSISTOR DEVICE
Provided is a power transistor device including a substrate structure, a first conductive layer, a second conductive layer and a third conductive layer. The...
2019/0043858 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first...
2019/0043857 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate,...
2019/0043856 ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING SELF-BIASING BURIED LAYER AND METHOD THEREFOR
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major...
2019/0043855 LINEARITY AND LATERAL ISOLATION IN A BiCMOS PROCESS THROUGH COUNTER-DOPING OF EPITAXIAL SILICON REGION
Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type...
2019/0043854 ESD DEVICE WITH FAST RESPONSE AND HIGH TRANSIENT CURRENT
An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a...
2019/0043853 SEMICONDUCTOR DEVICE
Provided is a semiconductor device having an ESD protection diode and a vertical MOSFET in which desired ESD tolerance is obtained without reducing the active...
2019/0043852 MONOLITHICALLY INTEGRATED SEMICONDUCTOR SWITCH, IN PARTICULAR A POWER CIRCUIT BREAKER
In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected...
2019/0043851 SEMICONDUCTOR DEVICE
To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a...
2019/0043850 DESIGN FOR MANUFACTURABILITY (DFM) CELLS IN EXTREME ULTRA VIOLET (EUV) TECHNOLOGY
Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes...
2019/0043849 SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least...
2019/0043848 SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME
A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first...
2019/0043847 CONNECTION SYSTEM OF SEMICONDUCTOR PACKAGES
A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed...
2019/0043846 A PACKAGING DEVICE FOR INTEGRATED POWER SUPPLY SYSTEM AND PACKAGING METHOD THEREOF
The present disclosure provides a packaging device for an integrated power supply system and a packaging method thereof. The packaging device comprises: a...
2019/0043845 DISPLAY MODULE AND SYSTEM APPLICATIONS
A display module and system applications including a display module are described. The display module may include a display substrate including a front...
2019/0043844 MICRO LIGHT EMITTING DIODE DISPLAY PANEL
A micro light emitting diode display panel including a substrate, a plurality of control elements, and a plurality of light emitting units is provided. The...
2019/0043843 METHODS FOR MANUFACTURING A DISPLAY DEVICE
Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also...
2019/0043842 BI-DIRECTIONAL OPTICAL MODULE AND TRANSPARENT DISPLAY APPARATUS USING THE SAME
A bi-directional optical module includes a substrate, at least one first light-emitting diode (LED), and at least one second LED. The first LED is disposed on...
2019/0043841 SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS
A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip,...
2019/0043840 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUBSTRATE EXTENSIONS
Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package...
2019/0043839 SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first...
2019/0043838 FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK
A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s)...
2019/0043837 RADIO FREQUENCY SYSTEM-IN-PACKAGE WITH STACKED CLOCKING CRYSTAL
A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and...
2019/0043836 THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING WAFER-TO-WAFER BONDING
Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access...
2019/0043835 CONNECTION SYSTEM OF SEMICONDUCTOR PACKAGES
A connection system of semiconductor packages includes: a printed circuit board having a first surface, and a second surface, opposing the first surface; a...
2019/0043834 SEMICONDUCTOR PACKAGES HAVING INDICATION PATTERNS
A semiconductor package includes a package substrate, a first semiconductor chip on the package substrate, an encapsulant layer covering the first...
2019/0043833 SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF STACKED DIES
A semiconductor package includes core dies and an encapsulant layer. The core dies are stacked on a base die to leave edge regions of the base die exposed. The...
2019/0043832 THREE DIMENSIONAL CHIP STRUCTURE IMPLEMENTING MACHINE TRAINED NETWORK
Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at...
2019/0043831 SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked...
2019/0043830 THREE-DIMENSIONAL MEMORY DEVICE EMPLOYING DIRECT SOURCE CONTACT AND HOLE CURRENT DETECTION AND METHOD OF MAKING...
A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the...
2019/0043829 SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate...
2019/0043828 SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLCSP
A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a...
2019/0043827 SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor module includes: a semiconductor device having a front-side electrode; a bonding wire having a bonding portion bonded to the front-side...
2019/0043826 SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD
A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact...
2019/0043825 SEMICONDUCTOR DEVICE
According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first transistor, a second...
2019/0043824 Thermal Bonding Sheet, Thermal Bonding Sheet with Dicing Tape, Bonded Body Production Method, and Power...
A thermal bonding sheet includes a pre-sintering layer containing copper particles and polycarbonate.
2019/0043823 NEGATIVE FILLET FOR MOUNTING AN INTEGRATED DEVICE DIE TO A CARRIER
In some embodiments, an electronic module is disclosed. The electronic module can include a carrier and an integrated device die having an upper surface, a...
2019/0043822 QUBIT DIE ATTACHMENT USING PREFORMS
Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary...
2019/0043821 Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect
A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a...
2019/0043820 POWER ELECTRONICS ASSEMBLY HAVING AN ADHESION LAYER, AND METHOD FOR PRODUCING SAID ASSEMBLY
A power electronics method and assembly produced by the method. The assembly has a substrate, having a power semiconductor element, and an adhesion layer...
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