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Patent # Description
2019/0043768 Methods for Fabricating Semiconductor Devices Using a Fringe Signal
Methods for fabricating semiconductor devices are provided including forming a stacked structure including a first mold layer and a second mold layer on a...
2019/0043767 METHODS FOR MANUFACTURING A DISPLAY DEVICE
Methods for manufacturing a display device are provided. A representative method includes: providing a substrate having a plurality of sub-pixel locations;...
2019/0043766 HYBRID CORRECTIVE PROCESSING SYSTEM AND METHOD
A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data...
2019/0043765 CRITICAL DIMENSION CONTROL BY USE OF A PHOTO AGENT
A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the...
2019/0043764 SEMICONDUCTOR DEVICES AND MANUFACTURING TECHNIQUES FOR REDUCED ASPECT RATIO OF NEIGHBORING GATE ELECTRODE LINES
When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material...
2019/0043763 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a...
2019/0043762 FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function...
2019/0043761 SEMICONDUCTOR DEVICE
A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a...
2019/0043760 SEMICONDUCTOR STRUCTURE HAVING A BUMP AND A WIDTH OF THE BUMP LARGER THAN A WIDTH OF FIN SHAPED STRUCTURES, AND...
A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped...
2019/0043759 DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT
The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed...
2019/0043758 METHODS OF FORMING A GATE STRUCTURE-TO-SOURCE/DRAIN CONDUCTIVE CONTACT AND THE RESULTING DEVICES
Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative...
2019/0043757 Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches
A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage...
2019/0043756 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor...
2019/0043755 PROCESS FOR PRODUCING CONNECTIONS TO AN ELECTRONIC CHIP
The invention relates to aA process for producing conductive connections to an electronic chip, comprising the following steps: a) depositing an insulating...
2019/0043754 CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LINE TO VIA
A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a...
2019/0043753 METHOD FOR PROCESSING TARGET OBJECT
In a method for processing a target object, the target object includes a wiring layer having a wiring, a diffusion barrier film provided on the wiring layer,...
2019/0043752 TECHNIQUE FOR DEFINING ACTIVE REGIONS OF SEMICONDUCTOR DEVICES WITH REDUCED LITHOGRAPHY EFFORT
In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and...
2019/0043751 Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming...
2019/0043750 ROBOT DIAGNOSING METHOD
A robot diagnosing method detects a deviation amount caused by a lost motion and includes: a first step of preparing a robot including a robot arm having at...
2019/0043749 LITHOGRAPHIC APPARATUS, METHOD FOR UNLOADING A SUBSTRATE AND METHOD FOR LOADING A SUBSTRATE
A method for unloading a substrate from a support table configured to support the substrate, the method including: supplying gas to a gap between a base...
2019/0043748 ADHESIVE RESIN COMPOSITION FOR SEMICONDUCTOR, ADHESIVE FILM FOR SEMICONDUCTOR, AND DICING DIE BONDING FILM
The present invention relates to an adhesive resin composition for a semiconductor, including: a (meth)acrylate-based resin including a (meth)acrylate-based...
2019/0043747 FLEXIBLE CIRCUIT INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
Techniques and mechanisms for providing flexible packaged circuit structures. In an embodiment, a flexible circuit device includes first and second conductive...
2019/0043746 CERAMIC MATERIAL AND ELECTROSTATIC CHUCK DEVICE
Provided is a composite sintered body for an electrostatic chuck, which is not easily broken even if it is exposed to high-power plasma. Further, provided are...
2019/0043745 Flux-free solder ball mount arrangement
A system for the flux free processing of a plurality of solder balls on a wafer, comprising: an articulable vacuum support chuck for maintaining support of a...
2019/0043744 ACTIVE MONITORING SYSTEM FOR SUBSTRATE BREAKAGE PREVENTION
A method and apparatus for monitoring substrate lift pin operation is disclosed and includes a support pedestal for a vacuum chamber, the support pedestal...
2019/0043743 LASER PROCESSING APPARATUS
A laser processing apparatus has a control unit including an inspection modified layer former detecting a provisional orientation flat of a bare wafer and...
2019/0043742 SUBSTRATE PROCESSING SYSTEM
A measurement processing process S103 of measuring a cut width of a film based on an image obtained by imaging, with an imaging unit 270, a peripheral portion...
2019/0043741 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
The present disclosure relates to a substrate processing apparatus and a substrate processing method. The substrate processing apparatus according to the...
2019/0043740 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM
Disclosed is a substrate processing apparatus including: a substrate holding member that holds a peripheral portion of a substrate; a rotating member that...
2019/0043739 SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM
A substrate processing method includes: supplying a treatment liquid to a substrate held in a horizontal position; substituting the treatment liquid supplied...
2019/0043738 SUBSTRATE TRANSPORTING DEVICE, SUBSTRATE TREATING APPARATUS, AND SUBSTRATE TRANSPORTING METHOD
Disclosed is a substrate transporting device including a transport mechanism, a transport chamber, a first exhaust fan, and a controller. The transport...
2019/0043737 THERMAL MANAGEMENT OF INTEGRATED CIRCUITS
A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a...
2019/0043736 METHOD OF PRODUCING ELECTROCONDUCTIVE SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICE
A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base...
2019/0043735 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND METHOD FOR CUTTING Cu ALLOY
A method for manufacturing a semiconductor package by preparing a lead frame including a to-be-cut portion containing a Cu alloy; applying a joining material...
2019/0043734 ELECTRONICS PACKAGE WITH INTEGRATED INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THEREOF
An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating...
2019/0043733 ELECTRONICS PACKAGE WITH INTEGRATED INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THEREOF
An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate,...
2019/0043732 HIGH ASPECT RATIO SELECTIVE LATERAL ETCH USING CYCLIC PASSIVATION AND ETCHING
Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method...
2019/0043731 TWO-STAGE BAKE PHOTORESIST WITH RELEASABLE QUENCHER
Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable...
2019/0043730 METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH DAMASCENE STRUCTURE
A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer...
2019/0043729 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having...
2019/0043728 INTEGRATED ATOMIC LAYER PASSIVATION IN TCP ETCH CHAMBER AND IN-SITU ETCH-ALP METHOD
A method for etching a substrate includes performing, in a plasma chamber, a first etch of a substrate material using a plasma etch process. The first etch...
2019/0043727 GERMANIUM ETCHING SYSTEMS AND METHODS
Exemplary methods for etching a germanium-containing material may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a...
2019/0043726 PROCESS WINDOW WIDENING USING COATED PARTS IN PLASMA ETCH PROCESSES
Embodiments of the present technology may include a method of etching. The method may include mixing plasma effluents with a gas in a first section of a...
2019/0043724 DIFFUSING AGENT COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE
A diffusing agent composition that can efficiently form a thin film in which an impurity diffusion component can be diffused into a semiconductor substrate at...
2019/0043723 METHOD OF ENHANCED SELECTIVITY OF HARD MASK USING PLASMA TREATMENTS
Implementations described herein generally relate to an etching process for etching materials with high selectivity. In one implementation, a method of etching...
2019/0043722 SUBSTRATE TREATMENT METHOD, COMPUTER STORAGE MEDIUM AND SUBSTRATE TREATMENT SYSTEM
A substrate treatment method of performing a plurality of predetermined treatments on a substrate to form a plurality of patterns stacked on the substrate, the...
2019/0043721 METHOD OF ETCHING MULTILAYERED FILM
A method of etching a multilayered film including multiple silicon oxide films and multiple silicon nitride films is provided. A mask containing carbon is...
2019/0043720 MANUFACTURING SYSTEM AND METHOD FOR FORMING A CLEAN INTERFACE BETWEEN A FUNCTIONAL LAYER AND A TWO-DIMENSIONAL...
A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps...
2019/0043719 Method and Apparatus for Forming Silicon Film
A method of forming a silicon film in a recess formed in a target substrate includes: preparing a target substrate having a recess in which a plurality of...
2019/0043718 Mono- and Multilayer Silicene Prepared by Plasma-Enhanced Chemical Vapor Deposition
Processes for fabricating multi- and monolayer silicene on catalyst metal surfaces by means of plasma-enhanced chemical vapor deposition (PECVD). Silicene is...
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