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Patent # Description
2019/0042552 IDENTIFYING AND MAPPING EMOJIS
A computer system associates one or more actions with an emoji. The computer system detects a selection of the emoji within an electronic communication by a...
2019/0042551 APPARATUS AND METHOD FOR PROVIDING SUMMARIZED INFORMATION USING AN ARTIFICIAL INTELLIGENCE MODEL
An artificial intelligence system using a machine learning algorithm for providing summary information of a document input to an artificial intelligence...
2019/0042550 METHODS AND COMPUTING DEVICE FOR GENERATING MARKUP LANGUAGE TO REPRESENT A CALCULATION RELATIONSHIP
One or more computing devices carry out a method for generating markup language to represent a calculation relationship among facts, wherein each fact is...
2019/0042549 METHOD AND APPARATUS FOR BUILDING PAGES, APPARATUS AND NON-VOLATILE COMPUTER STORAGE MEDIUM
The present disclosure provides a method and apparatus for building pages, an apparatus and a non-volatile computer storage medium. According to embodiments of...
2019/0042548 METHODS FOR ARBITRATING ONLINE DISPUTES AND ANTICIPATING OUTCOMES USING MACHINE INTELLIGENCE
Methods for conflict arbitration and resolution anticipation through machine intelligence learning are provided herein. Methods for hypothesizing by a machine...
2019/0042547 INTEGRATED DOCUMENT EDITOR
A computing device includes a memory and a touch screen for displaying one or more text characters or graphic objects stored in the memory, and for detecting...
2019/0042546 UNIFIED GRAPHICAL USER INTERFACE VIEWS THROUGH FRAME BREAK OUT
When executing a feature of a frame (HTML document), a web browser utilizes a method for adjusting the size of the frame. The method includes expanding the...
2019/0042545 SYSTEM AND METHOD FOR DETERMINING SENSOR MARGINS AND/OR DIAGNOSTIC INFORMATION FOR A SENSOR
Systems and techniques for determining sensing margins and/or diagnostic information associated with a sensor are presented. A statistics component generates...
2019/0042544 FP16-S7E8 MIXED PRECISION FOR DEEP LEARNING AND OTHER ALGORITHMS
Disclosed embodiments relate to mixed-precision vector multiply-accumulate (MPVMAC) In one example, a processor includes fetch circuitry to fetch a compress...
2019/0042543 MATRIX DECOMPOSITION DEVICE AND MATRIX DECOMPOSITION METHOD
A matrix decomposition device extracts information on positions where elements become 1 in a matrix having, as an element, an absolute value of a difference...
2019/0042542 ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix...
2019/0042541 SYSTEMS, METHODS, AND APPARATUSES FOR DOT PRODUCT OPERATIONS
Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed....
2019/0042540 SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory...
2019/0042539 ACCELERATOR FOR MATRIX DECOMPOSITION
Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits...
2019/0042538 ACCELERATOR FOR PROCESSING DATA
An accelerator for increasing the processing speed of a processor. The accelerator operates in two distinct modes. In a first mode for dense layer processing,...
2019/0042537 METHOD AND APPARATUS FOR CONCURRENT READING AND CALCULATION OF MIXED RADIX DFT/IDFT
A method for concurrent reading of mixed radix DFT/IDFT data, a method for concurrent calculation of mixed radix DFT/IDFT method, an apparatus for concurrent...
2019/0042536 Subspace-Constrained Partial Update Method For High-Dimensional Adaptive Processing Systems
A method is explained for any adaptive processor processing digital signals by adjusting signal weights on digital signal(s) it handles, to optimize adaptation...
2019/0042535 SIDE-BY-SIDE DIESEL UTILITY VEHICLE
A utility vehicle comprises a plurality of ground engaging members and a frame supported by the plurality of ground engaging members. The frame includes a...
2019/0042534 SIGNAL PATHWAYS IN MULTI-TILE PROCESSORS
Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the...
2019/0042533 INTERFACE DISCOVERY BETWEEN PARTITIONS OF A PROGRAMMABLE LOGIC DEVICE
Systems, methods, and devices for enhancing the flexibility of an integrated circuit device with partially reconfigurable regions are provided. For example, a...
2019/0042532 SECURE SEMICONDUCTOR CHIP AND OPERATING METHOD THEREOF
A semiconductor chip may comprise: a processor for processing data; a shield which includes a metal line and is arranged over an upper portion of the...
2019/0042531 COMPUTER SYSTEM AND MOTHERBOARD THEREOF
A motherboard includes a multilayer printed circuit board (PCB), a central processing unit (CPU) slot, at least one first memory slot, at least one second...
2019/0042530 MULTI-DIRECTION CONNECTABLE ELECTRONIC MODULE AND MODULAR ELECTRONIC BUILDING SYSTEM
A multi-direction connectable electronic module includes a circuit board, including a top surface, a bottom surface, and at least one side; and a plurality of...
2019/0042529 Dynamic Deep Learning Processor Architecture
Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep...
2019/0042528 DYNAMIC ASSOCIATION OF APPLICATION WORKLOAD TIERS TO INFRASTRUCTURE ELEMENTS IN A CLOUD COMPUTING ENVIRONMENT
Embodiments of the present invention provide a method, system and computer program product for the dynamic association of components in a multi-tier...
2019/0042527 TECHNIQUES FOR COLLECTIVE OPERATIONS IN DISTRIBUTED SYSTEMS
Various embodiments are generally directed to techniques for collective operations among compute nodes in a distributed processing set, such as by utilizing...
2019/0042526 System, Apparatus And Method For Controlling Duty Cycle Of A Clock Signal For A Multi-Drop Interconnect
In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first...
2019/0042525 METHODS AND APPARATUS FOR TRANSMITTING TIME SENSITIVE DATA OVER A TUNNELED BUS INTERFACE
Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor...
2019/0042524 NEGOTIATING ASYMMETRIC LINK WIDTHS DYNAMICALLY IN A MULTI-LANE LINK
Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first...
2019/0042523 MANAGEMENT OF PRIORITY OF DATA TRANSMISSION ON A BUS
An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port...
2019/0042522 DATA RATE-ADAPTIVE DATA TRANSFER BETWEEN MODEMS AND HOST PLATFORMS
Systems, methods, and computer-readable media for transferring data between a host platform and modem circuitry are provided. At low data rates, data may be...
2019/0042521 ASYMMETRICAL EMBEDDED UNIVERSAL SERIAL BUS (EUSB) LINK
A Universal Serial Bus (USB) circuitry of an apparatus is disclosed. In an example, the USB circuitry includes a High Speed (HS) transmitter to transmit data...
2019/0042520 OUT-OF-BAND MANAGEMENT OF DATA DRIVES
Out-of-band management of data drives including receiving, from a user, a control command targeting a data drive communicatively coupled to a backplane,...
2019/0042519 Host Controller Apparatus, Host Controller Device, and Method for a Host Controller for Determining Information...
A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an...
2019/0042518 PLATFORM INTERFACE LAYER AND PROTOCOL FOR ACCELERATORS
There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function...
2019/0042517 SUPERIMPOSING BUTTERFLY NETWORK CONTROLS FOR PATTERN COMBINATIONS
A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many ...
2019/0042516 METHODS AND APPARATUS FOR PROGRAMMING AN INTEGRATED CIRCUIT USING A CONFIGURATION MEMORY MODULE
An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets...
2019/0042515 SYSTEM DECODER FOR TRAINING ACCELERATORS
There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively...
2019/0042514 MICRO-ARCHITECTURAL TECHNIQUES TO MINIMIZE COMPANION DIE FIRMWARE LOADING TIMES IN A SERVER PLATFORM
Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of...
2019/0042513 APPARATUSES, METHODS, AND SYSTEMS FOR OPERATIONS IN A CONFIGURABLE SPATIAL ACCELERATOR
Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial...
2019/0042512 SYSTEMS AND METHODS FOR INTERCONNECTING GPU ACCELERATED COMPUTE NODES OF AN INFORMATION HANDLING SYSTEM
An information handling system includes first and second compute nodes, each compute node including a central processing unit (CPU), a computational...
2019/0042511 NON VOLATILE MEMORY MODULE FOR RACK IMPLEMENTATIONS
An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory...
2019/0042510 TIMER CONTROL FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS COMPONENTS IMPLEMENTED WITH THUNDERBOLT CONTROLLERS
Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured...
2019/0042509 SYSTEMS AND METHODS FOR MODULAR EXPANSION IN DATA STORAGE LIBRARIES
Systems and methods are described herein for modular expansion of data storage libraries. In one or more embodiments, an apparatus for modularly expanding a...
2019/0042508 MULTI-UPLINK DEVICE ENUMERATION AND MANAGEMENT
A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to...
2019/0042507 ADAPT LINK TRAINING BASED ON SOURCE CAPABILITY INFORMATION
A source device includes an adaptive link training circuity. The link training circuitry includes source capability information for link training of a link...
2019/0042506 NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION
A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device...
2019/0042505 Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second...
2019/0042504 TECHNOLOGIES FOR FAST MAUSB ENUMERATION
Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative...
2019/0042502 MOBILE BROADBAND INTERFACE MODEL (MBIM) WITH TIMEOUT MECHANISM
Embodiments of the present disclosure are directed toward identifying an indication of a timeout related to a mobile broadband interface model (MBIM) process....
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