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Patent # Description
2019/0042501 TECHNOLOGIES FOR COMPUTATIONAL STORAGE VIA OFFLOAD KERNEL EXTENSIONS
Technologies for data processing or computation on data storage devices include a data storage controller. The data storage controller is configured to receive...
2019/0042500 DIMM FOR A HIGH BANDWIDTH MEMORY CHANNEL
A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
2019/0042499 HIGH BANDWIDTH DIMM
A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a...
2019/0042498 ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS
A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or...
2019/0042497 HUB CIRCUIT FOR A DIMM HAVING MULTIPLE COMPONENTS THAT COMMUNICATE WITH A HOST
An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second...
2019/0042496 DELAYED LINK COMPRESSION SCHEME
Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are...
2019/0042495 Method, Apparatus And System For Device Transparent Grouping Of Devices On A Bus
In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O...
2019/0042494 Techniques For Accelerating Memory Access Operations
A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to...
2019/0042493 READ PERFORMANCE ON A SATA STORAGE DEVICE BEHIND A HOST BUS ADAPTER
Examples may include a storage device coupled to a host bus adapter and a SATA controller over a SATA interface. The storage device includes a memory and a...
2019/0042492 REFERENCE VOLTAGE CALIBRATION USING A QUALIFIED WEIGHTED AVERAGE
An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may...
2019/0042491 Cache Coherent, High-Throughput Input/Output Controller
Input/output controllers and methods of operation thereof that may provide high-throughput data services to processing circuitry is described. The input/output...
2019/0042490 Memory Device, a Dual Inline Memory Module, a Storage Device, an Apparatus for Storing, a Method for Storing, A...
Examples provide a memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine...
2019/0042489 METHODS AND SYSTEMS FOR STREAMING DATA PACKETS ON PERIPHERAL COMPONENT INTERCONNECT (PCI) AND ON-CHIP BUS...
A method and architecture to write data between a source and destination by memory mapped writes or streaming packets between any of a host, a peripheral or a...
2019/0042488 SHARED MEMORY CONTROLLER IN A DATA CENTER
Technology for a memory controller is described. The memory controller can receive a request from a data consumer node in a data center for training data. The...
2019/0042487 HIGH-BANDWIDTH, LOW-LATENCY, ISOCHORONOUS FABRIC FOR GRAPHICS ACCELERATOR
Techniques are provided for low-latency, high bandwidth graphics accelerator die and memory system. In an example, a graphics accelerator die can include a...
2019/0042486 TECHNIQUES FOR COMMAND ARBITATION IN SYMMETRIC MULTIPROCESSOR SYSTEMS
A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an...
2019/0042485 TECHNOLOGIES FOR TRUSTED I/O SUPPORT FOR I/O DEVICES USING EXTERNAL PERIPHERAL DEVICE LINK CONTROLLER
Technologies for secure I/O with an external peripheral device link controller include a computing device coupled to an external dock device by an external...
2019/0042484 CONNECTING AN EXTERNAL PHY DEVICE TO A MAC DEVICE USING A MANAGEMENT DATA INPUT/OUTPUT INTERFACE
Examples include connecting an external physical layer device to a media access control device by determining a mode of a communications link between the...
2019/0042483 METHODS AND APPARATUS TO OFFLOAD MEDIA STREAMS IN HOST DEVICES
An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral...
2019/0042482 INTEGRATION OF DISPARATE SYSTEM ARCHITECTURES USING CONFIGURABLE ISOLATED MEMORY REGIONS AND TRUST DOMAIN...
Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security...
2019/0042481 PROCESS-BASED MULTI-KEY TOTAL MEMORY ENCRYPTION
Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to...
2019/0042480 METHOD FOR NON-VOLATILE MEMORY AND MEMORY CONTROLLER SECURED AND AUTHENTICATED PAIRING
Examples include techniques for determining validity of a memory used with a memory controller. Examples include a system having a memory device including a...
2019/0042479 HEURISTIC AND MACHINE-LEARNING BASED METHODS TO PREVENT FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS
A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a...
2019/0042478 Computer System and Method for Executing One or More Software Applications, Host Computer Device and Method for...
A computer system for executing one or more software applications includes a host computer device configured to execute the one or more software applications....
2019/0042477 SECURING DATA DIRECT I/O FOR A SECURE ACCELERATOR INTERFACE
The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various...
2019/0042476 LOW OVERHEAD INTEGRITY PROTECTION WITH HIGH AVAILABILITY FOR TRUST DOMAINS
Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing...
2019/0042475 SYSTEMS, METHODS AND APPARATUS FOR LOW LATENCY MEMORY INTEGRITY MAC FOR TRUST DOMAIN EXTENSIONS
The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment,...
2019/0042474 ENHANCED STORAGE ENCRYPTION WITH TOTAL MEMORY ENCRYPTION (TME) AND MULTI-KEY TOTAL MEMORY ENCRYPTION (MKTME)
This disclosure is directed to a processing device including a memory to store data, processing circuitry to process data, the processing circuitry including a...
2019/0042473 TECHNOLOGIES FOR ENABLING SLOW SPEED CONTROLLERS TO USE HW CRYPTO ENGINE FOR I/O PROTECTION
Technologies for secure I/O include a computing device that further includes an I/O controller and a trusted I/O (TIO) mode manager. The TIO mode manager is to...
2019/0042472 USE-AFTER-FREE EXPLOIT PREVENTION ARCHITECTURE
Various systems and methods for memory management are described herein. A system for managing memory includes a memory management unit to: receive an...
2019/0042471 TECHNOLOGIES FOR A LEAST RECENTLY USED CACHE REPLACEMENT POLICY USING VECTOR INSTRUCTIONS
Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device...
2019/0042470 METHOD OF DIRTY CACHE LINE EVICTION
Examples may include techniques to improve cache performance in a computing system. An eviction service may be used to manage a dirty list and a clean list,...
2019/0042469 MINIMIZING CACHE LATENCIES USING SET PREDICTORS
A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The...
2019/0042468 MINIMIZING CACHE LATENCIES USING SET PREDICTORS
A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The...
2019/0042467 SCALABLE PROCESSOR-ASSISTED GUEST PHYSICAL ADDRESS TRANSLATION
Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set...
2019/0042466 SUPPORTING MEMORY PAGING IN VIRTUALIZED SYSTEMS USING TRUST DOMAINS
Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of...
2019/0042465 VIRTUAL TRANSFER OF DATA BETWEEN MEMORY AND STORAGE DOMAINS
Devices, systems, and methods for transferring data between the memory domain and the storage domain are described. Transferring data between domains can...
2019/0042464 ADDRESS RANGE MAPPING FOR STORAGE DEVICES
Apparatuses, systems, methods, and computer program products are disclosed for address range mapping for memory devices. A system includes a set of...
2019/0042463 APPARATUS AND METHOD FOR SECURE MEMORY ACCESS USING TRUST DOMAINS
Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one...
2019/0042462 CHECKPOINTING FOR DRAM-LESS SSD
Methods and apparatus related to checkpointing for Solid State Drives (SSDs) that include no DRAM (Dynamic Random Access Memory) are described. In one...
2019/0042461 PAUSE COMMUNICATION FROM I/O DEVICES SUPPORTING PAGE FAULTS
A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page...
2019/0042460 METHOD AND APPARATUS TO ACCELERATE SHUTDOWN AND STARTUP OF A SOLID-STATE DRIVE
A computer system that includes a host based byte addressable persistent buffer to store a Logical to Physical (L2P) indirection table for a solid-state drive...
2019/0042459 STORAGE INFRASTRUCTURE FOR EXPLOITING IN-STORAGE TRANSPARENT COMPRESSION
A system, method and program product for exploiting in-storage transparent compression. A storage infrastructure is disclosed that includes: a storage device...
2019/0042458 DYNAMIC CACHE PARTITIONING IN A PERSISTENT MEMORY MODULE
Cache on a persistent memory module is dynamically allocated as a prefetch cache or a write back cache to prioritize read and write operations to a persistent...
2019/0042457 CACHE (PARTITION) SIZE DETERMINATION METHOD AND APPARATUS
Apparatuses, methods and storage medium associated with workload working set size determination, are disclosed herein. In embodiments, at least one...
2019/0042456 MULTIBANK CACHE WITH DYNAMIC CACHE VIRTUALIZATION
There is disclosed in one example a computing system, including: a processor including one or more computing cores; a cache having n discrete cache banks of...
2019/0042455 GLOBALLY ADDRESSABLE MEMORY FOR DEVICES LINKED TO HOSTS
Systems, methods, and devices can include ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled...
2019/0042454 TECHNIQUES TO MANAGE CACHE RESOURCE ALLOCATIONS FOR A PROCESSOR CACHE
Examples include techniques to manage cache resource allocations associated with one or more cache class of service (CLOS) assignments for a processor cache....
2019/0042453 HARDWARE BASED TECHNIQUE TO PREVENT CRITICAL FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS
A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality...
2019/0042452 CACHE UTILIZATION OF BACKING STORAGE FOR AGGREGATE BANDWIDTH
An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory,...
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