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Patent # Description
2019/0042451 EFFICIENT USAGE OF BANDWIDTH OF DEVICES IN CACHE APPLICATIONS
A memory storage control apparatus, system, and method are described. An apparatus can include a memory controller configured to couple to a primary memory...
2019/0042450 CACHE FILTER
The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a...
2019/0042449 MEMORY WITH REDUCED EXPOSURE TO MANUFACTURING RELATED DATA CORRUPTION ERRORS
A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line...
2019/0042448 SYSTEMS, METHODS, AND APPARATUSES UTILIZING CPU STORAGE WITH A MEMORY REFERENCE
Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a...
2019/0042447 IMPEDING MALICIOUS OBSERVATION OF CPU CACHE OPERATIONS
The present disclosure is directed to systems and methods for preventing or mitigating the effects of a cache-timing based side channel attack, such as a...
2019/0042446 MITIGATION OF CACHE-LATENCY BASED SIDE-CHANNEL ATTACKS
Particular embodiments described herein provide for an electronic device that can be configured to receive a request for data, wherein the request is received...
2019/0042445 TECHNOLOGIES FOR CACHING PERSISTENT TWO-LEVEL MEMORY DATA
Technologies for caching persistent two-level memory (2LM) data include a memory and a processor. The memory includes a volatile memory device and a...
2019/0042444 ADAPTIVE CALIBRATION OF NONVOLATILE MEMORY CHANNEL BASED ON PLATFORM POWER MANAGEMENT STATE
A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access...
2019/0042443 DATA ACQUISITION WITH ZERO COPY PERSISTENT BUFFERING
Examples may include techniques to manage data in a data acquisition system including allocating memory in a first stage buffer; storing data received by a...
2019/0042442 DATA STORAGE SYSTEM WITH PHYSICAL STORAGE AND CACHE MEMORY
A data storage system comprises physical storage, cache memory and a processor connected to the physical storage and the cache memory. The processor is...
2019/0042441 INTELLIGENT PREFETCH DISK-CACHING TECHNOLOGY
Systems, apparatuses and methods may provide for technology to automatically identify a plurality of non-volatile memory locations associated with a file in...
2019/0042440 OBJECT STORAGE SYSTEM WITH MULTI-LEVEL HASHING FUNCTION FOR STORAGE ADDRESS DETERMINATION
A method performed by a first hardware element in a hierarchical arrangement of hardware elements in an object storage system is described. The method includes...
2019/0042439 VICTIM CACHE LINE SELECTION
A set-associative cache memory includes a plurality of ways and a plurality of congruence classes. Each of the plurality of congruence classes includes a...
2019/0042438 REDUCING LATENCY BY CACHING DERIVED DATA AT AN EDGE SERVER
To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata...
2019/0042437 MEMORY CONTROLLER WITH PRE-LOADER
Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer...
2019/0042436 TECHNIQUES FOR PREFETCHING DATA TO A FIRST LEVEL OF MEMORY OF A HIERARCHICAL ARRANGEMENT OF MEMORY
Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the...
2019/0042435 HIGH-BANDWIDTH PREFETCHER FOR HIGH-BANDWIDTH MEMORY
A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer ("ORB"). The method stores in an address field of...
2019/0042434 DYNAMIC PREFETCHER TUNING
There is disclosed in one example a server apparatus for use in a data center, including: a processor having a memory prefetcher; a memory; a memory bus to...
2019/0042433 INSTRUCTION PREFETCH MECHANISM
An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch...
2019/0042432 REDUCING CACHE LINE COLLISIONS
There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache...
2019/0042431 TECHNOLOGIES FOR SECURE I/O WITH MIPI CAMERA DEVICE
Technologies for secure I/O with MIPI camera devices include a computing device having a camera controller coupled to a camera and a channel identifier filter....
2019/0042430 TECHNIQUES TO PROVIDE CACHE COHERENCY BASED ON CACHE TYPE
Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one...
2019/0042429 ADAPTIVE COHERENCE FOR LATENCY-BANDWIDTH TRADEOFFS IN EMERGING MEMORY TECHNOLOGIES
Examples include a processor including a coherency mode indicating one of a directory-based cache coherence protocol and a snoop-based cache coherency...
2019/0042428 TECHNIQUES FOR REQUESTING DATA ASSOCIATED WITH A CACHE LINE IN SYMMETRIC MULTIPROCESSOR SYSTEMS
A technique for operating a data processing system includes transitioning, by a cache, to a highest point of coherency (HPC) for a cache line in a required...
2019/0042427 RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY
A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory...
2019/0042426 INFORMATION PROCESSING APPARATUS AND METHOD
An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address...
2019/0042425 MANAGEMENT OF COHERENT LINKS AND MULTI-LEVEL MEMORY
Techniques for managing multi-level memory and coherency using a unified page granular controller can simplify software programming of both file system...
2019/0042424 METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION
A system and method for providing storage virtualization (SV) is disclosed. According to one embodiment, a system includes a storage device having a tier 1...
2019/0042423 DATA CENTER ENVIRONMENT WITH CUSTOMIZABLE SOFTWARE CACHING LEVELS
A method is described. The method includes configuring different software programs that are to execute on a computer with customized hardware caching service...
2019/0042422 CACHE ARCHITECTURE USING WAY ID TO REDUCE NEAR MEMORY TRAFFIC IN A TWO-LEVEL MEMORY SYSTEM
One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores...
2019/0042421 MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD
A memory control apparatus including at least one buffer memory and a processor coupled to the at least one buffer memory, and the processor configured to...
2019/0042420 MEMORY CARD WITH VOLATILE AND NON VOLATILE MEMORY SPACE HAVING MULTIPLE USAGE MODEL CONFIGURATIONS
An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory...
2019/0042419 TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a...
2019/0042418 POWER BUTTON OVERRIDE FOR PERSISTENT MEMORY ENABLED PLATFORMS
A power button override allows a persistent memory enabled platform to preserve data in persistent memory before initiating shutdown in a manner that is...
2019/0042417 SELECTIVE EXECUTION OF CACHE LINE FLUSH OPERATIONS
The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush...
2019/0042416 NON-VOLATILE MEMORY AWARE CACHING POLICIES
In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home...
2019/0042415 STORAGE MODEL FOR A COMPUTER SYSTEM HAVING PERSISTENT SYSTEM MEMORY
A processor is described. The processor includes register space to accept input parameters of a software command to move a data item out of computer system...
2019/0042414 NVDIMM EMULATION USING A HOST MEMORY BUFFER
Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a...
2019/0042413 METHOD AND APPARATUS TO PROVIDE PREDICTABLE READ LATENCY FOR A STORAGE DEVICE
A host based Input/Output (I/O) scheduling system that improves read latency by reducing I/O collisions and improving I/O determinism of storage devices is...
2019/0042412 METHOD AND APPARATUS TO IMPROVE SHARED MEMORY EFFICIENCY
Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared...
2019/0042411 LOGICAL OPERATIONS
In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory...
2019/0042410 FLEXIBLE BUFFER SIZING IN GRAPHICS PROCESSORS
Enhanced data buffer control in data systems is presented herein. In one example, a method of handling data buffer resources in a graphics processor includes...
2019/0042409 INTERLEAVE SET AWARE OBJECT ALLOCATION
An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of...
2019/0042408 TECHNOLOGIES FOR INTERLEAVING MEMORY ACROSS SHARED MEMORY POOLS
Technologies for interleaving memory that is accessible via a shared memory pool include a memory sled. The memory sled includes a memory pool of...
2019/0042407 RESILIENCY GROUPS
A method of operating a storage system is provided. The method includes detecting differing amounts of storage memory on two or more of a plurality of blades...
2019/0042406 SYSTEM AND METHOD TO MANAGE AND SHARE MANAGED RUNTIME MEMORY FOR JAVA VIRTUAL MACHINE
A method and system for self-regulating memory of a JAVA virtual machine optimizes memory use by the JVM and by an operating system. A computer running a...
2019/0042405 STORING DATA BASED ON WRITING FREQUENCY IN DATA STORAGE SYSTEMS
Systems and methods for segregate data in data storage system memory based on writing frequency are disclosed. In some embodiments, infrequently written data...
2019/0042404 ALLOCATING SHARED MEMORY BLOCKS TO TABLE ENTRIES TO STORE IN A MEMORY DEVICE
Provided are an apparatus and method for allocating shared memory blocks to table entries to store in a memory device. A memory interface unit includes...
2019/0042403 ORDERING OF MEMORY DEVICE MAPPING TO REDUCE CONTENTION
An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory...
2019/0042402 SYSTEM, APPARATUS AND METHOD FOR PROVIDING KEY IDENTIFIER INFORMATION IN A NON-CANONICAL ADDRESS SPACE
In one embodiment, an apparatus includes a page miss handler to receive a full address including a linear address portion having a linear address and a key...
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