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Patent # Description
2019/0042298 TECHNOLOGIES FOR ADAPTIVE PLATFORM RESOURCE ASSIGNMENT
Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a...
2019/0042297 TECHNOLOGIES FOR DEPLOYING VIRTUAL MACHINES IN A VIRTUAL NETWORK FUNCTION INFRASTRUCTURE
Technologies for deploying virtual machines (VMs) in a virtual network function (VNF) infrastructure include a compute device configured to collect a plurality...
2019/0042296 Technologies For Securing Data Structures For Controlling Virtual Machines
A data processing system with technology to secure a virtual machine control data structure (VMCDS) comprises random access memory (RAM) and a processor in...
2019/0042295 TIMING COMPENSATION FOR A TIMESTAMP COUNTER
Particular embodiments described herein provide for an electronic device that can be configured to receive a request for a timestamp associated with a virtual...
2019/0042294 System and method for implementing virtualized network functions with a shared memory pool
A method and system for implementing virtualized network functions (VNFs) in a network. Physical resources of the network are abstracted into virtual resource...
2019/0042293 TECHNOLOGIES FOR DYNAMIC STATISTICS MANAGEMENT
Technologies for dynamic statistics management include a computing device with a network interface controller (NIC) and a compute engine having a memory. The...
2019/0042292 TECHNOLOGIES FOR APPLICATION-SPECIFIC NETWORK ACCELERATION WITH UNIFIED COHERENCY DOMAIN
Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a...
2019/0042291 INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREFOR, AND PROGRAM
An information processing apparatus which is capable of carrying out asynchronous processes. In an MSP provided with an execution environment in which one...
2019/0042290 DYNAMICALLY CONFIGURABLE MICROSERVICE MODEL FOR DATA ANALYSIS USING SENSORS
A virtualized execution environment is generated for an analytic engine that includes executable code to implement an analytic model for processing an input...
2019/0042289 DEPLOYMENT AND MANAGEMENT PLATFORM FOR MODEL EXECUTION ENGINE CONTAINERS
At an interface a first analytic model for processing data and a second analytic model for processing data are received. A first virtualized execution...
2019/0042288 PL/SQL LANGUAGE PARSING AT A VIRTUAL MACHINE
In some database systems, a user device may query for data records using a procedural language extension to structured query language (PL/SQL) call. However,...
2019/0042287 Container Runtime Support
Processes, machines, and manufactures involving adaptable containers that can be built and torn down more efficiently than VMs, may support various processes,...
2019/0042286 ANALYTIC MODEL EXECUTION ENGINE WITH INSTRUMENTATION FOR GRANULAR PERFORMANCE ANALYSIS FOR METRICS AND...
At an interface an analytic model for processing data is received. The analytic model is inspected to determine a language, an action, an input type, and an...
2019/0042285 SERVICE REQUEST SYSTEM AND METHOD USING SERVICE REQUEST DEVICE FOR MULTIPLE LANGUAGE SUPPORTED ROOM
Disclosed are a service request system and method using a service request device for a multiple language supported room, more particularly, a service request...
2019/0042284 GENERATING COMPONENT PAGES TO RENDER IN A CONFIGURATION PAGE IN A GRAPHICAL USER INTERFACE TO CONFIGURE A...
Provided are a computer program product, system, and method for generating component pages to render in a configuration page in a graphical user interface...
2019/0042283 SOFTWARE APPLICATION DELIVERY AND LAUNCHING SYSTEM
One embodiment allocates a first virtual memory; receives executable code of a first piece of software; writes the executable code of the first piece of...
2019/0042282 RUNTIME OPTIMIZATION OF CONFIGURABLE HARDWARE
A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at...
2019/0042281 SYSTEM, METHOD, AND APPARATUS FOR DVSEC FOR EFFICIENT PERIPHERAL MANAGEMENT
Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an...
2019/0042280 System, Apparatus And Method For Providing Hardware Feedback Information In A Processor
In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback...
2019/0042279 LOW LATENCY BOOT FROM ZERO-POWER STATE
An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer...
2019/0042278 Partitioning Flash And Enabling Flexible Boot With Image Upgrade Capabilities
Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first...
2019/0042277 TECHNOLOGIES FOR PROVIDING RUNTIME CODE IN AN OPTION ROM
Technologies for utilizing a runtime code present in an option read only memory (ROM) include a sled that includes a device having an option ROM with runtime...
2019/0042276 SERVICE PROCESSING SYSTEM, SERVICE PROCESSING METHOD, AND SERVICE UPDATE METHOD
A service processing system, a service processing method, and a service update method are provided. The service processing method includes: receiving a service...
2019/0042275 BOOTING A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY
Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile...
2019/0042274 DYNAMIC TIMER ADJUSTMENT TO IMPROVE PERFORMANCE AND INHIBIT LIVELOCK CONDITIONS
An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine...
2019/0042273 Framework for Providing Calibration Alerts Using Unified Type System
A rules engine is provided that can work with various heterogeneous calling applications. Such a rules engine can be part of a larger framework which, for...
2019/0042272 METHODS AND APPARATUS TO UTILIZE NON-VOLATILE MEMORY FOR COMPUTER SYSTEM BOOT
Methods, apparatus, systems and articles of manufacture are disclosed to utilize non-volatile memory for computer system boot. An example processor platform...
2019/0042271 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM
An apparatus includes an arithmetic circuit that performs a pipeline operation on first data as an input; and a determination circuit that determines, based on...
2019/0042270 PROCESSOR PACKAGE WITH OPTIMIZATION BASED ON PACKAGE CONNECTION TYPE
The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and...
2019/0042269 APPARATUS AND METHOD FOR GANG INVARIANT OPERATION OPTIMIZATIONS
An apparatus and method for efficiently processing invariant operations on a parallel execution engine. For example, one embodiment of a processor comprises: a...
2019/0042268 LOW-OVERHEAD, LOW-LATENCY OPERAND DEPENDENCY TRACKING FOR INSTRUCTIONS OPERATING ON REGISTER PAIRS IN A...
A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction...
2019/0042267 LOW-OVERHEAD, LOW-LATENCY OPERAND DEPENDENCY TRACKING FOR INSTRUCTIONS OPERATING ON REGISTER PAIRS IN A...
A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction...
2019/0042266 WIDE VECTOR EXECUTION IN SINGLE THREAD MODE FOR AN OUT-OF-ORDER PROCESSOR
Embodiments of the present invention include methods, systems, and computer program products for implementing wide vector execution in a single thread mode for...
2019/0042265 WIDE VECTOR EXECUTION IN SINGLE THREAD MODE FOR AN OUT-OF-ORDER PROCESSOR
Embodiments of the present invention include methods, systems, and computer program products for implementing wide vector execution in a single thread mode for...
2019/0042264 APPARATUS AND METHOD FOR SINGLE CHIP QUANTUM CONTROL STACK
Apparatus and method for a single chip quantum control stack. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction...
2019/0042263 SELECTIVE ACCESS TO PARTITIONED BRANCH TRANSFER BUFFER (BTB) CONTENT
The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Spectre type...
2019/0042262 METHOD AND APPARATUS FOR EFFICIENT MATRIX ALIGNMENT IN A SYSTOLIC ARRAY
An apparatus and method for efficient matrix alignment in a systolic array. For example, one embodiment of a processor comprises: a first set of physical tile...
2019/0042261 SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS
Disclosed embodiments relate to systems and methods for performing instructions specifying horizontal tile operations. In one example, a processor includes...
2019/0042260 SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS SPECIFYING TERNARY TILE LOGIC OPERATIONS
Disclosed embodiments relate to systems and methods for performing instructions specifying ternary tile operations. In one example, a processor includes fetch...
2019/0042259 Methods and apparatus to insert profiling instructions into a graphics processing unit kernel
Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes an entry point...
2019/0042258 PROCESSOR CORE SUPPORTING A HETEROGENEOUS SYSTEM INSTRUCTION SET ARCHITECTURE
Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an...
2019/0042257 SYSTEMS AND METHODS FOR PERFORMING MATRIX COMPRESS AND DECOMPRESS INSTRUCTIONS
Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction...
2019/0042256 SYSTEMS AND METHODS TO ZERO A TILE REGISTER PAIR
Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a...
2019/0042255 SYSTEMS AND METHODS TO STORE A TILE REGISTER PAIR TO MEMORY
Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to...
2019/0042254 SYSTEMS AND METHODS TO LOAD A TILE REGISTER PAIR
Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load...
2019/0042253 COUNTING ELEMENTS IN DATA ITEMS IN A DATA PROCESSING APPARATUS
An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count...
2019/0042252 RECONFIGURABLE MULTI-PRECISION INTEGER DOT-PRODUCT HARDWARE ACCELERATOR FOR MACHINE-LEARNING APPLICATIONS
A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An...
2019/0042251 COMPUTE-IN-MEMORY SYSTEMS AND METHODS
An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on...
2019/0042250 VARIABLE FORMAT, VARIABLE SPARSITY MATRIX MULTIPLICATION INSTRUCTION
Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and...
2019/0042249 HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION
Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an...
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