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Patent # Description
2019/0042146 NAND-BASED STORAGE DEVICE WITH PARTITIONED NONVOLATILE WRITE BUFFER
A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned,...
2019/0042145 METHOD AND APPARATUS FOR MULTI-LEVEL MEMORY EARLY PAGE DEMOTION
An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level....
2019/0042144 DISTRIBUTED STORAGE LOCATION HINTING FOR NON-VOLATILE MEMORIES
Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for...
2019/0042143 TECHNOLOGIES FOR LOGGING AND VISUALIZING STORAGE EVENTS
Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute...
2019/0042142 STATISTICS AND PRIORITY-BASED CONTROL FOR STORAGE DEVICE
An embodiment of a semiconductor apparatus may include technology to monitor one or more external performance indicators related to a workload impact on a...
2019/0042141 ON ACCESS MEMORY ZEROING
An embodiment of a semiconductor package apparatus may include technology to determine one or more filtered memory locations of a memory, determine if a read...
2019/0042140 MASS STORAGE DEVICE WITH HOST INITIATED BUFFER FLUSHING
An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer...
2019/0042139 MOVING AVERAGE VALID CONTENT ON SSD
An embodiment of a semiconductor apparatus may include technology to track defect information related to a persistent storage media, and determine a best next...
2019/0042138 Adaptive Data Migration Across Disaggregated Memory Resources
Devices and systems for distributing data across disaggregated memory resources is disclosed and described. An acceleration controller device can include an...
2019/0042137 MEMORY DEVICE WITH SEPARATE MEMORY CONTROLLERS FOR PROGRAM/ERASE AND READ OPERATIONS
Technology for a nonvolatile memory (NVM) device is described. The NVM device can include a NVM interface structurally configured to communicatively couple to...
2019/0042136 TECHNOLOGIES FOR DIVIDING MEMORY ACROSS SOCKET PARTITIONS
Technologies for dividing resources across partitions include a compute sled. The compute sled is to determine partitions among sockets of the compute sled....
2019/0042135 SYSTEMS AND METHODS FOR REDUNDANT ARRAY DATA ALIGNMENT
A data alignment (DA) computing device is communicatively coupled to a first and a second data storage device. The first data storage device stores an array of...
2019/0042134 STORAGE CONTROL APPARATUS AND DEDUPLICATION METHOD
Provided is a storage control apparatus including: a cache memory configured to include a first cache area that holds a hash value of a first data block...
2019/0042133 TECHNOLOGIES FOR PROVIDING ADAPTIVE DATA ACCESS REQUEST ROUTING IN A DISTRIBUTED STORAGE SYSTEM
Technologies for providing adaptive data access request routing in a distributed storage system include a compute device. The compute device includes a...
2019/0042132 MALLEABLE CONTROLLER FOR STORAGE PROTOCOLS
A semiconductor apparatus may include technology to identify two or more types of storage controller traffic, direct a first identified type of storage...
2019/0042131 DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER
In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a...
2019/0042130 PREFIX OPCODE METHOD FOR SLC ENTRY WITH AUTO-EXIT OPTION
A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC...
2019/0042129 TECHNOLOGIES FOR ADJUSTING THE PERFORMANCE OF DATA STORAGE DEVICES BASED ON TELEMETRY DATA
Technologies for adjusting the performance of data storage devices based on telemetry data include a compute device with a compute engine. The compute engine...
2019/0042128 TECHNOLOGIES DYNAMICALLY ADJUSTING THE PERFORMANCE OF A DATA STORAGE DEVICE
Technologies for dynamically adjusting the performance of a data storage device include an apparatus with a controller. The controller is configured to obtain...
2019/0042127 Configuration or Data Caching for Programmable Logic Device
An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include...
2019/0042126 TECHNOLOGIES FOR STORAGE DISCOVERY AND REALLOCATION
Technologies for storage discovery and reallocation include a compute device. The compute device is to receive, from a data storage sled, storage device data...
2019/0042125 EXTERNAL INDICATORS FOR ADAPTIVE IN-FIELD RECALIBRATION
In accordance with one implementation, a method for adaptive in-field recalibration includes detecting a potential environmental disturbance for a first...
2019/0042124 METHODS AND APPARATUS TO OPTIMIZE DYNAMIC MEMORY ASSIGNMENTS IN MULTI-TIERED MEMORY SYSTEMS
Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example...
2019/0042122 TECHNOLOGIES FOR EFFICIENTLY MANAGING ALLOCATION OF MEMORY IN A SHARED MEMORY POOL
Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of...
2019/0042121 POWER-BASED DYNAMIC ADJUSTMENT OF MEMORY MODULE BANDWIDTH
In embodiments, a memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to...
2019/0042120 APPARATUSES AND METHODS FOR ACCESSING HYBRID MEMORY SYSTEM
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a memory array...
2019/0042119 INTERNAL POWER ANALYZER FOR DATA STORAGE DEVICE
A data storage device includes a power input port, a nonvolatile memory module, a controller for the nonvolatile memory module, and a power analyzer...
2019/0042118 SIDE-CHANNEL ATTACK RESISTANT FUSE PROGRAMMING
The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the...
2019/0042117 TECHNIQUES TO PROVIDE RUN-TIME PROTECTIONS USING IMMUTABLE REGIONS OF MEMORY
Various embodiments are generally directed to an apparatus, method and other techniques for determining a region of the memory for which to store information,...
2019/0042116 TECHNIQUES FOR PREVENTING MEMORY CORRUPTION
Techniques and apparatus for preventing memory corruption events, such as use-after-free vents, are described. In one embodiment, for example, an apparatus at...
2019/0042115 SECURING EXCLUSIVE ACCESS TO A COPY OF A METADATA TRACK VIA A PROCESS WHILE THE METADATA TRACK IS HELD IN A...
In response to determining, by a storage controller, that a first process is to perform a write operation, a customer data track in a cache is configured for...
2019/0042114 SELECTIVE BACKGROUND DATA REFRESH FOR SSDs
An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on...
2019/0042113 SSD WITH PERSISTENT DRAM REGION FOR METADATA
An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an...
2019/0042112 DATA STORAGE DEVICE WITH DEFECTIVE DIE INDICATOR
Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the...
2019/0042111 METHOD AND APPARATUS FOR POWER-FAIL SAFE COMPRESSION AND DYNAMIC CAPACITY FOR A STORAGE DEVICE
Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile...
2019/0042110 DETECTING AND HANDLING SOLICITED IO TRAFFIC MICROBURSTS IN A FIBRE CHANNEL STORAGE AREA NETWORK
A Fibre Channel (FC) or FC-over-Ethernet (FCoE) switch has ports to forward Input-Output (TO) requests, and service data transfers, between end devices in a...
2019/0042109 WEAR LEVELING
In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear...
2019/0042108 NONVOLATILE MEMORY STORE SUPPRESION
An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory...
2019/0042107 WEAR LEVELING
In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear...
2019/0042106 EXTENDING SSD LONGEVITY
A storage appliance includes a first SSD, a second SSD, and a controller. The controller is able to calculate a first utilization parameter of the first SSD...
2019/0042105 HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE
Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced...
2019/0042104 TIER-OPTIMIZED WRITE SCHEME
A request to write data corresponding to at least a first portion of a file is received. It is determined whether to perform the request either as an in-place...
2019/0042103 RESILIENT EXTERNAL MEMORY
Methods and apparatuses may be provided, where data is written to a first region of memory on a first memory appliance in response to a write operation, the...
2019/0042102 MEMORY SCHEDULING METHOD FOR CHANGING COMMAND ORDER AND METHOD OF OPERATING MEMORY SYSTEM
Disclosed is a method of operating a memory system which executes a plurality of commands including a write command and a trim command. The memory system...
2019/0042101 Quality of Service Management in a Distributed Storage System
One or more computing devices may comprise congestion management circuitry, one or more client file system request buffers, and DESS interface circuitry. The...
2019/0042100 APPARATUS AND METHODS FOR A DISTRIBUTED MEMORY SYSTEM INCLUDING MEMORY NODES
Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system...
2019/0042099 APPARATUS, METHOD, AND PROGRAM PRODUCT FOR DATA INTEGRITY DURING ASYNCHRONOUS REMOTE COPY
A system, method, and program product are disclosed for asynchronous remote copy. One method includes transmitting a write request to a remote primary storage...
2019/0042098 REDUCTION OF WRITE AMPLIFICATION OF SSD WITH INTEGRATED MEMORY BUFFER
An embodiment of a semiconductor apparatus may include technology to define a region for a backed-up portion of a volatile memory, and designate the region as...
2019/0042097 NON-VOLATILE MEMORY CLONING WITH HARDWARE COPY-ON-WRITE SUPPORT
Examples may include a non-volatile memory having a memory including a first table of device physical addresses and a second table of physical device...
2019/0042096 PROVIDING TRACK FORMAT INFORMATION WHEN MIRRORING UPDATED TRACKS FROM A PRIMARY STORAGE SYSTEM TO A SECONDARY...
Provided are a computer program product, system, and method for providing track format information when mirroring updated tracks from a primary storage system...
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