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Patent # Description
2019/0057970 HIGH COUPLING RATIO SPLIT GATE MEMORY CELL
A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator...
2019/0057969 SELF ALIGNED ACTIVE TRENCH CONTACT
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill...
2019/0057968 DEVICE COMPRISING CAPACITOR AND FORMING METHOD THEREOF
A device including a capacitor includes an isolation structure, a first control gate, a first selective gate and a first dielectric layer. The isolation...
2019/0057967 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME
A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in...
2019/0057966 SEMICONDUCTOR DEVICES
A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel...
2019/0057965 FINFET AND MANUFACTURING METHOD OF THE SAME
A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain...
2019/0057964 Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric
An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a...
2019/0057963 MOS TRANSISTORS IN PARALLEL
An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating...
2019/0057962 SEMICONDUCTOR STRUCTURE AND DESIGN METHOD OF DUMMY PATTERN LAYOUT
A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and...
2019/0057961 HIGH HOLDING HIGH VOLTAGE (HHHV) FET FOR ESD PROTECTION WITH MODIFIED SOURCE AND METHOD FOR PRODUCING THE SAME
A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include...
2019/0057960 SEMICONDUCTOR DEVICE HAVING ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE
Disclosed is a semiconductor device having an e1ectrostatic discharge protection structure. The e1ectrostatic discharge protection structure is a diode...
2019/0057959 SEMICONDUCTOR DEVICE AND STRUCTURE WITH THERMAL ISOLATION
A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a...
2019/0057958 OPTOELECTRONIC APPARATUS
An optoelectronic apparatus is provided having a carrier device that has at least one optoelectronic transmitter and/or at least one optoelectronic receiver at...
2019/0057957 AUGMENTED REALITY DISPLAY SYSTEM
There is disclosed a transparent light field display device including a transparent substrate, an array of light-emitting picture elements formed on the...
2019/0057956 ELECTRONIC MODULE
An electronic module comprising a first electronic unit 51 which has a first insulating substrate 61 and a first electronic element 41 provided on the first...
2019/0057955 VIDEO WALL MODULE AND METHOD OF PRODUCING A VIDEO WALL MODULE
A video wall module includes a plurality of light emitting diode chips, each including first contact electrodes and second contact electrodes arranged at a...
2019/0057954 LIGHT EMITTING DIODES, COMPONENTS AND RELATED METHODS
A light emitter device includes a submount with a top surface and a bottom surface, electrically conductive traces on the top surface of the submount, light...
2019/0057953 APPARATUS AND METHOD FOR MULTI-DIE INTERCONNECTION
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a...
2019/0057951 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG
A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a...
2019/0057950 PERMANENT FUNCTIONAL CARRIER SYSTEMS AND METHODS
An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device...
2019/0057949 SEMICONDUCTOR PACKAGES
A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold...
2019/0057948 CHIP PACKAGE STRUCTURE
A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an...
2019/0057947 MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side...
2019/0057946 Polymer Layers Embedded with Metal Pads for Heat Dissipation
An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation...
2019/0057945 A Transition Arrangement Comprising a Contactless Transition or Connection Between an SIW and a Waveguide or an...
The present invention relates to a transition arrangement (100) comprising a transition between a substrate integrated waveguide, SIW, (20) of a circuit...
2019/0057944 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating...
2019/0057943 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device comprises a substrate, a die, an encapsulant and an antenna layer. The substrate has a top surface and a bottom surface opposite...
2019/0057942 INTEGRATED CIRCUIT WITH AN EMBEDDED INDUCTOR OR TRANSFORMER
In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one...
2019/0057941 INTEGRATED SHIELD PACKAGE AND METHOD
An integrated shield electronic component package includes a substrate having as upper surface, a lower surface, and sides extending between the upper surface...
2019/0057940 STAIRSTEP INTERPOSERS WITH INTEGRATED SHIELDING FOR ELECTRONICS PACKAGES
Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may...
2019/0057939 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment...
2019/0057938 CHIP ON GLASS PACKAGE ASSEMBLY
A chip on glass package assembly includes a glass substrate, a first type chip, a second type chip and a plurality of connecting lines. The glass substrate...
2019/0057937 HYBRID MICROELECTRONIC SUBSTRATE AND METHODS FOR FABRICATING THE SAME
A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic...
2019/0057936 TRANSMISSIVE COMPOSITE FILM FOR APPLICATION TO THE BACKSIDE OF A MICROELECTRONIC DEVICE
A transmissive composite film is described that may be applied to the backside of a microelectronic device, for example an integrated circuit die or a bridge....
2019/0057935 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure is disclosed. The semiconductor structure includes a first interlayer dielectric (ILD) layer disposed on a semiconductor substrate. A...
2019/0057934 REDISTRIBUTION LAYER STRUCTURE OF SEMICONDUCTOR PACKAGE
A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a...
2019/0057933 Fan-Out Wafer Level Package Structure
A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the...
2019/0057932 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a molding surrounding the first...
2019/0057931 PACKAGE METHOD FOR GENERATING PACKAGE STRUCTURE WITH FAN-OUT INTERFACES
A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module...
2019/0057930 SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING SAME
A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with...
2019/0057929 THROUGH-MOLD OPENINGS FOR DUAL-SIDED PACKAGED MODULES WITH BALL GRID ARRAYS
Modules, devices and methods of manufacturing a dual-sided module are disclosed. A dual-sided module includes a packaging substrate having an upper side, a...
2019/0057928 POWER SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREFOR
A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is...
2019/0057927 COMPONENT COUPLED TO HEAT DISSIPATION UNIT
A component coupled to a heat dissipation unit, allowing a screwing element to be pivotally coupled to a heat dissipation unit, includes a body, a stop...
2019/0057926 HEAT DISSIPATION SHEET, MANUFACTURING METHOD OF HEAT DISSIPATION SHEET, AND ELECTRONIC APPARATUS
A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon...
2019/0057924 SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME
A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna;...
2019/0057923 Assembly and Method for Mounting an Electronic Component to a Substrate
In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic...
2019/0057922 WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE
The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with...
2019/0057921 ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
In an electronic device including an electronic component, a sealing resin body, a first member having at least a portion located in the sealing resin body,...
2019/0057920 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a...
2019/0057919 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable...
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