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Patent # Description
2019/0081011 METHOD FOR DETECTING THINNING OF AN INTEGRATED CIRCUIT SUBSTRATE VIA ITS REAR FACE, AND CORRESPONDING...
An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via...
2019/0081010 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
The present invention discloses a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a...
2019/0081009 SEMICONDUCTOR PACKAGE HAVING AN ELECTRO-MAGNETIC INTERFERENCE SHIELDING OR ELECTRO-MAGNETIC WAVE SCATTERING...
Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that...
2019/0081008 CHIP WITH CIRCUIT FOR DETECTING AN ATTACK ON THE CHIP
A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control...
2019/0081007 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a semiconductor element, and a first member. The first member includes a first magnetic planar...
2019/0081006 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a first surface, which includes an element forming region and an element isolation region, and...
2019/0081005 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER
According to an embodiment, a first resist pattern that includes a mark including a second pattern provided with first components and a third pattern not...
2019/0081004 DIE IDENTIFICATION BY OPTICALLY READING SELECTIVELY BLOWABLE FUSE ELEMENTS
Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to...
2019/0081003 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package is described. The semiconductor package includes a substrate, a line trace, a solder resist and an organic film. The line trace...
2019/0081002 SEMICONDUCTOR PACKAGES WITH EMBEDDED BRIDGE INTERCONNECTS
Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor...
2019/0081001 Dielectric Film Forming Composition
This disclosure relates to dielectric film forming compositions containing a) at least one fully imidized polyimide polymer; b) at least one metal-containing...
2019/0081000 CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal...
2019/0080998 SEMICONDUCTOR DEVICES WITH INSULATED SOURCE/DRAIN JUMPER STRUCTURES
A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin...
2019/0080997 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first...
2019/0080996 CHIP-ON-FILM PACKAGE STRUCTURE
A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible...
2019/0080995 SUBSTRATE FOR PACKAGING A SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a...
2019/0080994 PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A package substrate and a semiconductor package are provided. The package substrate including a substrate body having a first surface on which a semiconductor...
2019/0080993 SUBSTRATE AND SEMICONDUCTOR DEVICE PACKAGE
A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer...
2019/0080992 POWER MODULE FOR AN ELECTRIC MOTOR
A power module for an electric motor has at least one semiconductor switch half bridge with a high-side semiconductor switch and a low-side semiconductor...
2019/0080991 LEAD FRAME HAVING REDISTRIBUTION LAYER
Embodiments of a packaged semiconductor device are provided, which includes a flag of a lead frame having a top surface and a bottom surface; a redistribution...
2019/0080990 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections,...
2019/0080989 CONDUCTIVE CLIP CONNECTION ARRANGEMENTS FOR SEMICONDUCTOR PACKAGES
Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements...
2019/0080988 SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device capable of being miniaturized and preventing reduction of mountability to a wiring substrate. The...
2019/0080987 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first...
2019/0080986 SEMICONDUCTOR APPARATUS, IGNITION DEVICE FOR INTERNAL COMBUSTION ENGINE, AND INTERNAL COMBUSTION ENGINE SYSTEM
An end of a high-voltage electrode (5) is connected to a high-voltage terminal of a semiconductor device (1). An end of a low-voltage electrode (6) is...
2019/0080985 LIQUID-COOLED TYPE COOLING DEVICE
A liquid-cooled type cooling device includes first and second casings which are capable of being divided in a vertical direction. On a bottom wall part of the...
2019/0080984 LIQUID-COOLED TYPE COOLING DEVICE
In a liquid-cooled type cooling device, fins are accommodated in the interior of a casing having a supply port and a discharge port, and electronic components...
2019/0080983 Cryogenic Integrated Circuit having a Heat Sink coupled to Separate Ground Planes through Differently Sized...
An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first...
2019/0080982 High Density Multi-Component Packages
Provided is a high density multi-component package and a method of manufacturing a high density multi-component package. The high density multi-component...
2019/0080981 THERMAL INTERFACE MATERIALS WITH WEAR-RESISTING LAYERS AND/OR SUITABLE FOR USE BETWEEN SLIDING COMPONENTS
Exemplary embodiments are disclosed of thermal interface materials with wear-resisting layers and/or suitable for use between sliding components. Also...
2019/0080980 SMD Package with Top Side Cooling
A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first...
2019/0080979 SEMICONDUCTOR DEVICE
A semiconductor device includes a circuit substrate having a first metal layer on a first side, a second metal later on a second side, and an insulating layer...
2019/0080978 ELECTROMAGNETIC WAVE ABSORBING HEAT CONDUCTIVE SHEET, METHOD FOR PRODUCING ELECTROMAGNETIC WAVE ABSORBING HEAT...
Disclosed is an electromagnetic wave absorbing heat conductive sheet having superior heat conductivity and electromagnetic wave absorbency. The electromagnetic...
2019/0080977 THROUGH ELECTRODE SUBSTRATE AND MANUFACTURING METHOD THEREOF
A through electrode substrate includes: a substrate; a first electrode part provided on a first surface side of the substrate; and a second electrode part...
2019/0080976 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an...
2019/0080975 MULTI-MOLDINGS FAN-OUT PACKAGE AND PROCESS
A semiconductor device package includes a semiconductor device, a conductive bump, a first encapsulant and a second encapsulant. The semiconductor device has a...
2019/0080974 ELECTRICAL CONNECTION STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
Various embodiments may provide an electrical connection structure. The electrical connection structure may include a first substrate having a first surface...
2019/0080973 SMD Package with Top Side Cooling
A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first...
2019/0080972 SEMICONDUCTOR DEVICE
A semiconductor device having a housing is provided, where the housing includes the first surface, concave portions provided to the first surface, the second...
2019/0080971 TESTING METHOD OF PACKAGING PROCESS AND PACKAGING STRUCTURE
A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit...
2019/0080970 REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYS
What disclosed are structures and methods for repairing emissive display systems. Various repairing techniques embodiments in accordance with the structures...
2019/0080969 SEMICONDUCTOR STRUCTURE WITH BURIED POWER RAIL, INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE...
A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a...
2019/0080968 METHOD OF FABRICATING FINS INCLUDING REMOVING DUMMY FINS AFTER FLUOROCARBON FLUSH STEP AND OXYGEN CLEAN STEP
A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the...
2019/0080967 ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing...
2019/0080966 MANUFACTURING A COMBINED SEMICONDUCTOR DEVICE
A method for manufacturing a combined semiconductor device. The method includes providing a semiconductor substrate, providing a protective layer or a...
2019/0080965 SEMICONDUCTOR DIE SINGULATION METHODS
Implementations of a method of singulating a plurality of die may include: providing a semiconductor wafer including a plurality of die located on a first side...
2019/0080964 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
Provided is a method of manufacturing a semiconductor device capable of dividing a wafer with metal formed on a rear surface thereof into individual pieces...
2019/0080963 VARIABLE STEALTH LASER DICING PROCESS
Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a...
2019/0080962 BONDING STRUCTURE, FLEXIBLE SCREEN WITH THE BONDING STRUCTURE AND MANUFACURING METHOD OF THE SAME
A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are...
2019/0080961 METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT STRUCTURE
The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a...
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