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Patent # Description
2019/0115343 SOURCE/DRAIN REGIONS IN FIN FIELD EFFECT TRANSISTORS (FINFETS) AND METHODS OF FORMING SAME
An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is...
2019/0115342 HIGH QUALITY FACTOR FIN METAL OXIDE SEMICONDUCTOR VARACTOR WITH IMPROVED NUMBER OF FINS
A FinMosVar (fin metal oxide semiconductor (MOS) varactor) has an improved number of fins. The number of fins are determined based on a measured or calculated...
2019/0115341 INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a...
2019/0115340 ELECTROSTATIC DISCHARGE PROTECTION APPARATUSES
Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a...
2019/0115339 CIRCUIT, SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
A circuit including a discharging device, a resistive element and a bypass device is disclosed. The discharging device is disposed between a first voltage bus...
2019/0115338 SEMICONDUCTOR DEVICE
An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of...
2019/0115337 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without...
2019/0115336 Method and Structure for Semiconductor Mid-End-Of-Year (MEOL) Process
A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active...
2019/0115335 DISPLAY DEVICE WITH A CHIP ON FILM
A display device including a display panel including a substrate, pixels provided on the substrate, and first lines connected to the pixels, the display device...
2019/0115334 SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME
A semiconductor apparatus includes a driver circuit wafer including a plurality of driver circuits arranged in an array, a bonding metal layer formed over the...
2019/0115333 DISPLAY APPARATUS
A display apparatus includes a driving substrate, a plurality of micro light-emitting devices, and a common electrode. The micro light-emitting devices are...
2019/0115332 Packages and Methods of Forming Packages
Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated...
2019/0115331 SUBSTRATE FOR SYSTEM IN PACKAGING (SIP) DEVICES
Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required...
2019/0115330 METHOD FOR FABRICATING ELECTRONIC PACKAGE
An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first...
2019/0115329 LED MODULE ASSEMBLIES FOR DISPLAYS
Disclosed is an LED module assembly for a display including a first LED module and a second LED module. The first LED module includes a first unit substrate, a...
2019/0115328 SEMICONDUCTOR DEVICE, DISPLAY PANEL, AND METHOD FOR MANUFACTURING DISPLAY PANEL
The semiconductor element according to an embodiment comprises: a light-emitting structure comprising a p-type semiconductor layer, an active layer disposed...
2019/0115327 Semiconductor Packages and Methods of Forming the Same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die...
2019/0115326 Semiconductor Packages having Dummy Connectors and Methods of Forming Same
An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit...
2019/0115324 FLEXIBLE LED FILAMENT AND ASSEMBLY THEREOF
A flexible LED filament having a flexible substrate composed of a metal layer and ceramic insulating layer. The metal layer forms a core of the flexible...
2019/0115323 CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES
Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die...
2019/0115322 3DIC Interconnect Apparatus and Method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is...
2019/0115321 Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a...
2019/0115320 Stacked Integrated Circuit Structure and Method of Forming
A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact...
2019/0115319 SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF
A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various...
2019/0115318 MODULAR VOLTAGE REGULATORS
A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed...
2019/0115317 MODULAR VOLTAGE REGULATORS
A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed...
2019/0115316 PACKAGING METHOD AND PACKAGE STRUCTURE OF WAFER-LEVEL SYSTEM-IN-PACKAGE
The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a...
2019/0115315 SEMICONDUCTOR LEADFRAMES AND PACKAGES WITH SOLDER DAMS AND RELATED METHODS
A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the...
2019/0115314 METHODS AND STRUCTURES FOR WAFER-LEVEL SYSTEM IN PACKAGE
The present disclosure provides a packaging method for wafer-level system in package. The packaging method for wafer-level system in package includes bonding...
2019/0115313 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a...
2019/0115312 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one...
2019/0115311 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant...
2019/0115310 COMPOSITE ANTENNA SUBSTRATE AND SEMICONDUCTOR PACKAGE MODULE
A composite antenna substrate and semiconductor package module includes: a fan-out semiconductor package including a semiconductor chip, an encapsulant...
2019/0115309 STACK ASSEMBLY HAVING ELECTRO-ACOUSTIC DEVICE
Stack assembly having electro-acoustic device. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a...
2019/0115308 DISTRIBUTING ON CHIP INDUCTORS FOR MONOLITHIC VOLTAGE REGULATION
Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators...
2019/0115307 Chip-on-Substrate Packaging on Carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a...
2019/0115306 METHOD FOR FORMING CHIP PACKAGE STRUCTURE
Methods for forming chip package structures are provided. The method includes disposing a first chip structure, a second chip structure over a carrier...
2019/0115305 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
The present disclosure provides for a semiconductor package device and a method for manufacturing the same. The semiconductor package device includes a...
2019/0115304 Eliminate Sawing-Induced Peeling Through Forming Trenches
A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top...
2019/0115303 OVERLAY MARK
A method of forming an overlay mark includes disposing a first feature of a plurality of first alignment segments extending along a first direction in a first...
2019/0115302 Oxide-Peeling Stopper
A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer...
2019/0115301 VISIBLE ALIGNMENT MARKERS/LANDMARKS FOR CAD-TO-SILICON BACKSIDE IMAGE ALIGNMENT
A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are...
2019/0115300 Multi-Stacked Package-on-Package Structures
A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the...
2019/0115299 Conductive Vias in Semiconductor Packages and Methods of Forming Same
An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant;...
2019/0115298 Passive Devices in Package-on-Package Structures and Methods for Forming the Same
A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the...
2019/0115297 Method of Forming Metal Interconnection
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first...
2019/0115296 SEMICONDUCTOR DEVICE
A first power supply terminal P is provided with an internal wiring connection portion 31A, an upright portion 31B which is joined to the internal wiring...
2019/0115295 SEMICONDUCTOR DEVICE
A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a...
2019/0115294 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device includes an interconnection structure, an electronic component, a package body and an electrical contact. The dielectric layer...
2019/0115293 MULTIPLE BALL GRID ARRAY (BGA) CONFIGURATIONS FOR A SINGLE INTEGRATED CIRCUIT (IC) PACKAGE
An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on...
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