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Patent # Description
2019/0123045 DEVICES RELATED TO BARRIER FOR METALLIZATION OF GALLIUM BASED SEMICONDUCTOR
Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some...
2019/0123044 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and...
2019/0123042 Integrated Circuit having a MOM Capacitor and Method of Making Same
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a...
2019/0123041 METHOD OF FORMING A HETEROJUNCTION SEMICONDUCTOR DEVICE HAVING INTEGRATED CLAMPING DEVICE
A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a...
2019/0123040 THIN-FILM ESD PROTECTION DEVICE
A thin-film ESD protection device that includes a semiconductor substrate having a first and second principal surfaces); a first insulating layer disposed on...
2019/0123039 LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR
A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on...
2019/0123038 High Voltage ESD Protection Apparatus
A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a...
2019/0123037 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a...
2019/0123036 SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK
Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure...
2019/0123035 METHOD OF PERFORMING DIE-BASED HETEROGENEOUS INTEGRATION AND DEVICES INCLUDING INTEGRATED DIES
A method for integrating heterogeneous elements with elements residing on a target wafer is described. A source die including a compound semiconductor...
2019/0123034 METHOD OF MANUFACTURING POWER SEMICONDUCTOR MODULE AND POWER SEMICONDUCTOR MODULE
A method of manufacturing a power semiconductor module according to the present invention includes the steps of: (a) forming a 6-in-1 chip 1 that is a power...
2019/0123033 Ultra-Dense LED Projector
A monolithic display/projector is disclosed comprising a single die having an array of mechanically isolated LED pillars. Each pillar has a height greater than...
2019/0123032 LIGHT EMITTING STRUCTURE
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a...
2019/0123031 ELASTOMERIC LAYER FABRICATION FOR LIGHT EMITTING DIODES
An elastomeric interface layer (elayer) is formed over multiple light emitting diode (LED) dies by depositing photoresist materials across multiple LED dies,...
2019/0123030 POWER MODULE AND METHOD FOR MANUFACTURING POWER MODULE
The present invention concerns a power module comprising at least one power die, the at least one power die is embedded in a multilayer structure, the...
2019/0123029 Package-on-Package (PoP) Device with Integrated Passive Device in a Via
A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the...
2019/0123028 3D Die Stacking Structure with Fine Pitches
A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package...
2019/0123027 Package-On-Package (PoP) Structure Including Stud Bulbs
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure...
2019/0123026 Stacked Semiconductor Structure and Method
A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric...
2019/0123025 INTEGRATED CIRCUIT PACKAGE ASSEMBLY
An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit...
2019/0123024 3D Processor
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at...
2019/0123023 3D Compute Circuit with High Density Z-Axis Interconnects
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at...
2019/0123022 3D Compute Circuit with High Density Z-Axis Interconnects
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at...
2019/0123021 Dual-Sided Integrated Fan-Out Package
A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein...
2019/0123020 Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and...
2019/0123019 Tri-Layer CoWoS Structure
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package...
2019/0123018 Methods for Controlling Warpage in Packaging
A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies...
2019/0123017 Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps
Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package...
2019/0123016 PACKAGE ASSEMBLY
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a...
2019/0123015 PRINTING MODULE, PRINTING METHOD AND SYSTEM OF FORMING A PRINTED STRUCTURE
A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to...
2019/0123014 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
There is disclosed a method for manufacturing a semiconductor device comprising a semiconductor chip having a connection portion and a wiring circuit board...
2019/0123013 Interposer Assembly
An interposer assembly having a housing with contact positioning holes each having a first wall face and a second wall face. The interposer contact has a base...
2019/0123012 SEMICONDUCTOR DEVICE
A semiconductor device including a first semiconductor switching element having a first gate pad, a plurality of first emitter pads, and a first collector pad,...
2019/0123011 SEMICONDUCTOR DEVICE
A semiconductor device according to the present invention includes a resist provided so as to have an opening on a metal pattern, the resist having a...
2019/0123010 SEMI-CONDUCTOR PACKAGE STRUCTURE
Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts,...
2019/0123009 SEMICONDUCTOR DEVICE
A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external...
2019/0123008 Bump on Pad (BOP) Bonding Structure in Semiconductor Packaged Device
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated...
2019/0123007 REDISTRIBUTION METAL AND UNDER BUMP METAL INTERCONNECT STRUCTURES AND METHOD
An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer...
2019/0123006 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a first substrate including a first surface, at least one first bonding pad disposed on the first surface, and at least one...
2019/0123005 MECHANICALLY ANCHORED C4 PAD AND METHOD OF FORMING SAME
The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse...
2019/0123004 METHOD OF FABRICATING AN INTEGRATED FAN-OUT PACKAGE
An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a...
2019/0123003 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the ...
2019/0123002 INTEGRALLY FORMED BIAS AND SIGNAL LEAD FOR A PACKAGED TRANSISTOR DEVICE
A lead, for a packaged transistor device, having a signal portion and a bias line portion, with the signal portion and the bias line portion each having a...
2019/0123001 Method and Apparatus of ESD Protection in Stacked Die Semiconductor Device
An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger...
2019/0123000 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode...
2019/0122999 Packaging Devices and Methods for Semiconductor Devices
Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging...
2019/0122998 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The semiconductor device includes a metal plate, a semiconductor element held on the metal plate, a wiring board connected to a surface electrode of the...
2019/0122997 SHIELDING FOR THROUGH-SILICON-VIA NOISE COUPLING
In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard...
2019/0122996 SEMICONDUCTOR STRUCTURE
A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and...
2019/0122995 PRINTED CIRCUIT BOARDS WITH ANTI-WARPING MOLDING PORTIONS AND RELATED SEMICONDUCTOR PACKAGES AND METHODS OF...
A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can...
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