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Patent # Description
2019/0132004 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2019/0132003 METHOD OF DETECTING AUDIO INPUT MODE
A method of detecting audio input mode applied to an electronic device is disclosed. According to how the user presses the start button of the electronic...
2019/0132002 DATA COMPRESSION AND DECOMPRESSION
Apparatus comprises data compression circuitry to process a set of data values, the data compression circuitry comprising: detector circuitry to detect, for...
2019/0132001 A COMPRESSING METHOD OF A GRAYSCALE COMPENSATION TABLE OF AN OLED DISPLAY PANEL
The disclosure provided a compressing method of the grayscale compensation table of an OLED display panel, which comprising: step 10, when transmitting a set...
2019/0132000 OPTICAL CAMERA COMMUNICATION APPARATUS AND METHOD
The present disclosure in some embodiments provides a transmit data structure and a communication method using the same, which can minimize the loss of the...
2019/0131999 MODULATOR FOR A DIGITAL AMPLIFIER
The present invention relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier. The modulator (100)...
2019/0131998 METHOD OF ARRANGING CAPACITOR ARRAY OF SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method...
2019/0131997 BOOTSTRAPPED HIGH-SPEED SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER
Apparatus, system and method for driving asynchronous digital-to-analog circuits are provided. An apparatus including circuitry configured to receive an analog...
2019/0131996 DIGITAL-TO-ANALOG CONVERTERS HAVING A RESISTIVE LADDER NETWORK
According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a...
2019/0131995 POLAR ANALOG-TO-DIGITAL CONVERTER AND DOWN CONVERTER FOR BANDPASS SIGNALS
Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the...
2019/0131994 HIGH-SPEED AND LOW-POWER PIPELINED ADC USING DYNAMIC REFERENCE VOLTAGE AND 2-STAGE SAMPLE-AND-HOLD
Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC...
2019/0131993 ADC SELF-TEST USING TIME BASE AND CURRENT SOURCE
A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the...
2019/0131992 BACKGROUND CALIBRATION OF REFERENCE, DAC, AND QUANTIZATION NON-LINEARITY IN ADCS
Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC...
2019/0131991 ANALOG-TO-DIGITAL CONVERTER AND CALIBRATION METHOD THEREOF AND CALIBRATION APPARATUS
A calibration method includes the following: providing a first charge quantity to a first input terminal of a comparator; providing a second charge quantity to...
2019/0131990 TRACK AND HOLD CIRCUITS FOR HIGH SPEED AND INTERLEAVED ADCS
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H...
2019/0131989 NOISE-SHAPING ANALOG-TO-DIGITAL CONVERTER
Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the...
2019/0131988 COMPARATOR ERROR SUPPRESSION
Comparator input noise or offset suppression can include an error detector circuit that can operate in a feedback loop, such as during an autozero phase. The...
2019/0131987 DA CONVERTER, DA CONVERTING METHOD, ADJUSTING APPARATUS, AND ADJUSTING METHOD
A DA converter to reduce second-order harmonic distortion more precisely with convenient configurations. ADA converter including: a DA converting unit to input...
2019/0131986 METHOD AND APPARATUS FOR OFFSET CORRECTION IN SAR ADC WITH REDUCED CAPACITOR ARRAY DAC
Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced...
2019/0131985 FREQUENCY SIGNAL GENERATION APPARATUS AND FREQUENCY SIGNAL GENERATION SYSTEM
A frequency signal generation apparatus includes an atom cell including a first part including gaseous alkali metal atoms and a second part including liquid...
2019/0131984 MICRO-RESONATOR-BASED FREQUENCY COMB TERAHERTZ ION CLOCK
An ion-based atomic clock comprising an ion trap configured to trap a plurality of ions; and a micro-resonator-based frequency comb configured to directly...
2019/0131983 FRACTIONAL CLOCK GENERATOR
A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog...
2019/0131982 METHOD AND ASSOCIATED SIGNAL SYSTEM IMPROVING MITIGATION OF INJECTION-PULLING EFFECT
The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock...
2019/0131981 APPARATUS COMPRISING A PHASE-LOCKED LOOP
There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal...
2019/0131980 SEMICONDUCTOR APPARATUS FOR PERFORMING CLOCK PHASE SYNCHRONIZATION, AND AN OPERATING METHOD THEREOF AND...
A semiconductor apparatus may include a synchronization circuit, and a phase detection circuit. The synchronization circuit may be configured to, based on an...
2019/0131979 Method And System For Phase Alignment Of Multiple Phased Locked Loops
A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1 . . . PLL_N) and a plurality N of...
2019/0131978 PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN...
A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator;...
2019/0131977 METHOD AND SYSTEM FOR PROVIDING A VARIATION RESISTANT MAGNETIC JUNCTION-BASED XNOR CELL USABLE IN NEUROMORPHIC...
A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of...
2019/0131976 POWER MANAGEMENT FOR MULTI-DIMENSIONAL PROGRAMMABLE LOGIC DEVICES
A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs...
2019/0131975 NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include...
2019/0131974 WIDTH AND FREQUENCY CONVERSION WITH PHY LAYER DEVICES IN PCI-EXPRESS
A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second...
2019/0131973 Programmable Shift Register With Programmable Load Location
Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register...
2019/0131972 APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICONDUCTOR DEVICE SHARING AN EXTERNAL RESISTANCE
Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a ...
2019/0131971 APPARATUS AND SYSTEM OF A LEVEL SHIFTER
Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first...
2019/0131970 Embedded FPGA with Multiple Configurable Flexible Logic Blocks Instantiated and Interconnected by Abutment
An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs...
2019/0131969 Elastomer-based Capacitive Control and Operating Element
A control and operating element has at least one dielectric elastomer sensor in which at least two electrode layers, between which a capacitance can be...
2019/0131968 SWITCH
A switch includes a substrate and a microwave line comprising two tracks produced on the substrate, an active zone of the substrate being bounded by the two...
2019/0131967 BUS DRIVER WITH RISE/FALL TIME CONTROL
A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal...
2019/0131966 SWITCHING DEVICE FOR CONDUCTING AND INTERRUPTING ELECTRICAL CURRENTS
A switching device for conducting and disconnecting electric currents includes: a first mechanical contact assembly; a semiconductor switch, which is in...
2019/0131965 RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET
The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the...
2019/0131964 POWER CIRCUIT
A power circuit has a power switching device (PSD) to, when in an ON state, conduct current from its first to second terminal; a diode anti-parallel to the PSD...
2019/0131963 CONTROL OF A PASS SWITCH BY A CURRENT SOURCE
In some examples, a controller is configured to control a power switch electrically connected in series with a winding. In some examples, the controller is...
2019/0131962 DUTY CYCLE DETECTOR AND PHASE DIFFERENCE DETECTOR
A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using...
2019/0131961 FRACTIONAL TIME DELAY STRUCTURES IN DIGITALLY OVERSAMPLED MICROPHONE SYSTEMS, CIRCUITS, AND METHODS
An apparatus to time delay a digital, signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first...
2019/0131960 GLITCH DETECTION IN INPUT/OUTPUT BUS
A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the...
2019/0131959 HIGH SPEED ON-CHIP PRECISION BUFFER WITH SWITCHED-LOAD REJECTION
A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a...
2019/0131958 CLOCK SKEW SUPPRESSION FOR TIME-INTERLEAVED CLOCKS
A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging...
2019/0131957 FILTER COEFFICIENT CALCULATION DEVICE, SIGNAL GENERATION DEVICE INCLUDING THE SAME, FILTER COEFFICIENT...
A filter coefficient calculation device includes a function unit that has a plurality of functions to be executed by an FIR filter, a function selection unit...
2019/0131956 REDUCED TRANSISTOR BRIDGE ATTENUATOR
An apparatus includes a bypass circuit a resistor circuit and multiple staggered circuits. The bypass circuit may have a predetermined number of a plurality of...
2019/0131955 ELASTIC WAVE ELEMENT AND ELASTIC WAVE FILTER DEVICE
An elastic wave element includes a piezoelectric substrate, an IDT electrode including a first comb-shaped electrode and a second comb-shaped electrode, and...
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