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Patent # Description
2019/0131447 Semiconductor Device with Termination Structure Including Field Zones and Method of Manufacturing
In termination regions of a silicon carbide substrate field zones are formed by ion implantation. By laterally modulating a distribution of dopants entering...
2019/0131446 Semiconductor Device with Junction Termination Zone
A semiconductor device includes a drift zone formed in a semiconductor portion. In a transition section of the semiconductor portion a vertical extension of...
2019/0131445 FIN PROFILE FOR BULK BASED SILICON-ON-INSULATION FINFET DEVICE
A semiconductor device includes a substrate, and a semiconductor fin structure formed on the substrate. The semiconductor device also includes a dielectric...
2019/0131444 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second...
2019/0131443 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second...
2019/0131442 SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer....
2019/0131441 HIGH HOLE MOBILITY TRANSISTOR
A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and...
2019/0131440 POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a...
2019/0131439 METHOD OF FORMING EPITAXIAL SILICON LAYER AND SEMICONDUCTOR DEVICE THEREOF
A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate...
2019/0131438 BIPOLAR TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE
Systems and methods are disclosed for processing radio frequency (RF) signals using one or more field-effect transistors disposed on or above a ...
2019/0131437 INTEGRATED CIRCUIT DIE HAVING BACK-END-OF-LINE TRANSISTORS
Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar...
2019/0131436 FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL),...
2019/0131435 APPROACH TO HIGH-K DIELECTRIC FEATURE UNIFORMITY
A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a...
2019/0131434 FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME
A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form...
2019/0131433 DUAL-CURVATURE CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH
Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a...
2019/0131432 SINGLE-CURVATURE CAVITY FOR SEMICONDUCTOR EPITAXY
Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region...
2019/0131431 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately...
2019/0131430 HYBRID SPACER INTEGRATION FOR FIELD-EFFECT TRANSISTORS
Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A...
2019/0131429 METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES
One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial...
2019/0131427 HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE
A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate....
2019/0131426 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the...
2019/0131425 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the...
2019/0131424 METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES
The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a...
2019/0131423 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The...
2019/0131422 CHEMICALLY SENSITIVE SENSOR WITH LIGHTLY DOPED DRAINS
A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor....
2019/0131421 SEMICONDUCTOR DEVICE STRUCTURE WITH SALICIDE LAYER AND METHOD FOR FORMING THE SAME
Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method...
2019/0131420 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the...
2019/0131419 INTEGRATED CIRCUIT METAL GATE STRUCTURE
A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal...
2019/0131418 CONFORMAL REPLACEMENT GATE ELECTRODE FOR SHORT CHANNEL DEVICES
A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor...
2019/0131417 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and...
2019/0131416 METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED
A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The...
2019/0131415 GATE-ALL-AROUND STRUCTURE AND MANUFACTURING METHOD FOR THE SAME
Present disclosure provides gate-all-around structure including a first transistor. The first transistor includes a semiconductor substrate having a top...
2019/0131414 PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES
A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region....
2019/0131413 FinFET with Two Fins on STI
A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the...
2019/0131412 SEMICONDUCTOR DEVICE
A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion...
2019/0131411 Method for Forming Source/Drain Contacts
Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a...
2019/0131410 THIN FILM TRANSISTOR, PRODUCTION METHOD THEREOF, AND ELECTRONIC APPARATUS
Provided is a thin film transistor, a production method thereof, and an electronic apparatus. The thin film transistor comprises a substrate, and a gate...
2019/0131409 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor...
2019/0131408 Semiconductor Interconnect Structure Having Graphene-Capped Metal Interconnects
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure...
2019/0131407 Artificial Synapse with Hafnium Oxide-Based Ferroelectric Layer in CMOS Front-End
Artificial synaptic devices with a HfO.sub.2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of...
2019/0131406 LDMOS FINFET STRUCTURES WITH SHALLOW TRENCH ISOLATION INSIDE THE FIN
Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second...
2019/0131405 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
Present disclosure provides a semiconductor structure including a first transistor and a second transistor. The first transistor includes a semiconductor...
2019/0131404 LOW GATE CURRENT JUNCTION FIELD EFFECT TRANSISTOR DEVICE ARCHITECTURE
A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased...
2019/0131403 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first...
2019/0131402 FINFET CASCODE LATERALLY-DIFFUSED SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant. The...
2019/0131401 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source/drain regions and a a threshold voltage adjusting region. The...
2019/0131400 SOI SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered ...
2019/0131399 Doping for Semiconductor Device with Conductive Feature
The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a...
2019/0131398 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating film. The...
2019/0131397 SCHOTTKY BARRIER DIODE
A Schottky barrier diode includes a first semiconductor layer having depressions on a top surface thereof, and having a guard ring extending from the top...
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