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Patent # Description
2019/0131294 SEMICONDUCTOR ELECTROSTATIC DISCHARGE PROTECTION DEVICE
The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first...
2019/0131293 ELECTROSTATIC DISCHARGE DEVICE
An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the...
2019/0131292 ELECTROSTATIC DISCHARGE PROTECTION USING VERTICAL FIN CMOS TECHNOLOGY
Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment,...
2019/0131291 Systems and Methods for a Sequential Spacer Scheme
Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target...
2019/0131290 LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS
A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical...
2019/0131289 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE
A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on...
2019/0131288 RECEIVER OPTICAL MODULE AND PROCESS OF ASSEMBLING THE SAME
A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module...
2019/0131287 Semiconductor Devices and Methods of Forming the Same
A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over...
2019/0131286 Method to Form a Stacked Electronic Structure
A stacked electronic structure comprises: a substrate and a magnetic device, wherein a plurality of electronic devices and a plurality of conductive pillars...
2019/0131285 FAN-OUT SEMICONDUCTOR PACKAGE MODULE
A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has...
2019/0131284 CHIP PACKAGE WITH INTERPOSER SUBSTRATE AND METHOD FOR FORMING THE SAME
A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a...
2019/0131283 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first...
2019/0131282 MICRO-LED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
A micro-LED display panel including a substrate, an anisotropic conductive film, and a plurality of micro-LEDs is provided. The anisotropic conductive film is...
2019/0131281 MICRO-LED DISPLAY PANEL
A micro-LED display panel including a substrate, a plurality of micro-LEDs, and a plurality of reinforced structures is provided. The micro-LEDs are disposed...
2019/0131280 Semiconductor Package for Thermal Dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed...
2019/0131279 Semiconductor Device and Method of Manufacture
A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two...
2019/0131278 MULTICHIP PACKAGING FOR DICE OF DIFFERENT SIZES
Apparatuses, methods and storage medium associated with integrated packaging for a stack of semiconductor dice of different sizes are disclosed herein. In...
2019/0131277 DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME AND PACKAGE
Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding...
2019/0131276 DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME
Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure...
2019/0131275 SEMICONDCUTOR DEVICE PACKAGE AND METHOD OF FORMING SEMICONDCUTOR DEVICE PACKAGE
A semiconductor device package includes a lower redistribution structure, an upper encapsulated semiconductor device and an upper redistribution structure. The...
2019/0131274 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a...
2019/0131273 MULTI-CHIP WAFER LEVEL PACKAGES AND METHODS OF FORMING THE SAME
Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The...
2019/0131272 Method for 3D Ink Jet TCB Interconnect Control
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The...
2019/0131271 CHIP BONDING APPARATUS, CHIP BONDING METHOD AND A CHIP PACKAGE STRUCTURE
A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place...
2019/0131270 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a...
2019/0131269 INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal...
2019/0131268 Innovative Interconnect Design for Package Architecture to Improve Latency
An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and...
2019/0131267 OPTICAL SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip...
2019/0131266 FABRICATION METHOD OF HIGH ASPECT RATIO SOLDER BUMPING WITH STUD BUMP AND INJECTION MOLDED SOLDER, AND FLIP...
A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is...
2019/0131265 CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME
An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit...
2019/0131264 Semiconductor Device Structure and Manufacturing Method
A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a...
2019/0131263 Conductive External Connector Structure and Method of Forming
External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical...
2019/0131262 INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant...
2019/0131261 PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a...
2019/0131260 3DI Solder Cup
A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder...
2019/0131259 METHOD OF FORMING A PASSIVATION LAYER
A method of forming a passivation layer on an integrated circuit (IC) chip including a device layer on a substrate. The method may include forming a...
2019/0131258 SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE
To enable a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has...
2019/0131257 SEMICONDUCTOR PACKAGE HAVING INDUCTIVE LATERAL INTERCONNECTS
Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the...
2019/0131256 MAGNETIC STRUCTURE FOR TRANSMISSION LINES IN A PACKAGE SYSTEM
A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the...
2019/0131255 SEAL RING FOR BONDED DIES
A device includes first and second dies and a seal ring. The first die includes a top dielectric layer. The second die is over the first die. The second die...
2019/0131254 Warpage Control in Package-on-Package Structures
A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a...
2019/0131253 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a...
2019/0131252 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip...
2019/0131251 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a semiconductor device, a first seal ring, a second seal ring, and a plurality of through semiconductor vias (TSV). The...
2019/0131250 Electromagnetic Interference Shield within Integrated Circuit Encapsulation Using Photonic Bandgap Structure
An encapsulated integrated circuit is provided that includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. An...
2019/0131249 METHOD FOR FORMING PACKAGE STRUCTURE
A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and...
2019/0131248 Display Device
The present disclosure relates to a display device including a first substrate and a second substrate facing each other; and a first identification number (ID)...
2019/0131247 Semiconductor Wafer Cutting Using A Polymer Coating To Reduce Physical Damage
Methods for providing a polymer coating on the scribe lines of a semiconductor wafer to reduce or eliminate chipping caused by mechanical saw cutting along the...
2019/0131246 THERMALLY ISOLATED GROUND PLANES WITH A SUPERCONDUCTING ELECTRICAL COUPLER
An integrated circuit is provided that comprises a first ground plane associated with a first set of circuits that have a first operational temperature...
2019/0131245 TRANSMISSION LINE STRUCTURE WITH HIGH Q FACTOR AND LOW INSERTION LOSS FOR MILLIMETER WAVE APPLICATIONS
The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure...
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