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Patent # Description
2019/0139903 FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending...
2019/0139902 ULTRA-THIN THERMALLY ENHANCED ELECTRO-MAGNETIC INTERFERENCE SHIELD PACKAGE
A method to fabricate an electronic package is described and includes the steps of: connecting a plurality of semiconductor chips to at least one surface of a...
2019/0139901 SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT
A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the...
2019/0139900 SEMICONDUCTOR PACKAGES INCLUDING DIE OVER-SHIFT INDICATING PATTERNS
A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die...
2019/0139899 SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN SHIELDING CORE PLATE
A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first...
2019/0139898 CHIP PACKAGE STRUCTURE AND CHIP PACKAGE STRUCTURE ARRAY
A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars,...
2019/0139897 PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is...
2019/0139896 PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection...
2019/0139895 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE LINE
A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer...
2019/0139894 BICONVEX LOW RESISTANCE METAL WIRE
At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or...
2019/0139893 Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Extending Conductor Laterally...
A method of forming an elevationally-extending conductor laterally between a pair of structures comprises forming a pair of structures individually comprising...
2019/0139892 VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME
One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a...
2019/0139891 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE
A method includes etching a semiconductor substrate to form a fin. An isolation structure is formed over the semiconductor substrate and around the fin. The...
2019/0139890 INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a...
2019/0139889 LOSSY MIM CAPACITOR FOR ON-DIE NOISE REDUCTION
According to certain aspects of the present disclosure, a semiconductor die includes a decoupling capacitor between a first interconnect metal layer and a...
2019/0139888 Package Structures and Method of Forming the Same
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least...
2019/0139887 DIELECTRIC HELMET-BASED APPROACHES FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION AND STRUCTURES...
Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a...
2019/0139886 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating...
2019/0139885 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a...
2019/0139884 COMBINED ELECTRODE AND THREE-LEVEL HIGH-POWER MODULE THEREOF
A combined electrode comprises a negative electrode, a first intermediate electrode, a positive electrode and a second intermediate electrode, wherein a main...
2019/0139883 PACKAGED SEMICONDUCTOR SYSTEM HAVING UNIDIRECTIONAL CONNECTIONS TO DISCRETE COMPONENTS
A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond...
2019/0139882 CIRCUIT ASSEMBLY AND MOUNTING UNIT
Each of busbars includes a bottom surface and a top surface. A holding member is made of resin and is formed integrally with the busbars. The bottom surface of...
2019/0139881 SECURITY DEVICE SUCH THAT A SMART CARD
A security device includes a body and a contact interface including an external connection for external communication and an internal connection for internal...
2019/0139880 Semiconductor Arrangement with Reliably Switching Controllable Semiconductor Elements
A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base...
2019/0139879 MULTI-ROW WIRING MEMBER FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating...
2019/0139878 METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS
An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive...
2019/0139877 PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD
A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the...
2019/0139876 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a...
2019/0139875 FLAT NO-LEAD PACKAGE WITH SURFACE MOUNTED STRUCTURE
The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure...
2019/0139874 SEMICONDUCTOR DEVICE HAVING TWO SWITCHING ELEMENTS
A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a...
2019/0139873 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor...
2019/0139872 PRESS-FIT PIN AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A press-fit pin increases contact area with the contact hole to provide appropriate contact pressure, reduce contact resistance, and increase heat transfer...
2019/0139871 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a...
2019/0139870 SEMICONDUCTOR PACKAGE
A semiconductor package is provided, including: a package body; and a plurality of lead terminals exposed from each of at least three side surfaces of the...
2019/0139869 Molded Semiconductor Package with C-Wing and Gull-Wing Leads
A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face...
2019/0139868 SEMICONDUCTOR DEVICES AND METHODS AND APPARATUS TO PRODUCE SUCH SEMICONDUCTOR DEVICES
Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame...
2019/0139867 CHIP ON FILM PACKAGE STRUCTURE
A chip on film (COF) package structure used to package a chip is disclosed. The COF package structure includes a flexible substrate, a conductive layer, a...
2019/0139866 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin...
2019/0139865 CHIP PACKAGE STRUCTURE
Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip...
2019/0139864 CAPPED THROUGH-SILICON-VIAs FOR 3D INTEGRATED CIRCUITS
The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a...
2019/0139863 COOLING APPARATUS
A cooling apparatus is provided with a casing having a top wall and a bottom wall and having a cooling fluid passage provided therein and a heat radiator...
2019/0139862 HEAT DISSIPATION APPARATUS AND METHOD FOR POWER SEMICONDUCTOR DEVICES
An improved heat dissipation apparatus for limiting the temperature of multiple power semiconductors featuring flow balancers to manipulate the hydrodynamic...
2019/0139861 STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR
An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The...
2019/0139860 PACKAGE STRUCTURE
A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating...
2019/0139859 POWER AND RF DEVICES IMPLEMENTED USING AN ENGINEERED SUBSTRATE STRUCTURE
An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic...
2019/0139858 SEMICONDUCTOR DEVICE
A first inner heat conductor may include a plurality of first graphite layers. A second inner heat conductor may include a plurality of second graphite layers....
2019/0139857 SYNTHETIC DIAMOND HEAT SPREADERS
A synthetic diamond heat spreader that includes a first layer of synthetic diamond material forming a base support layer and a second layer of synthetic...
2019/0139856 Ion-Implanted Thermal Barrier
Ion implantation can be used to define a thermal dissipation path that allows for better thermal isolation between devices in close proximity on a...
2019/0139855 ENHANCED SYSTEMS AND METHODS FOR IMPROVED HEAT TRANSFER FROM SEMICONDUCTOR PACKAGES
Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between...
2019/0139854 THERMAL-DISSIPATING SUBSTRATE STRUCTURE
A substrate structure is provided, including a substrate, an integrated circuit chip, a circuit structure, and a thermal-dissipating structure. The integrated...
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