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Patent # Description
2019/0139853 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing...
2019/0139851 SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER
A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads...
2019/0139850 Temporary Bonding Scheme
A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one...
2019/0139849 SEMICONDUCTOR PACKAGE INCLUDING A DEVICE AND LEAD FRAME USED FOR THE SAME
A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an...
2019/0139848 Configuring a Sealing Structure Sealing a Component Embedded in a Component Carrier for Reducing Mechanical Stress
A component carrier including a stack of at least one electrically conductive layer structure and at least one electrically insulating layer structure, a...
2019/0139847 PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A package structure and a method of manufacturing the same are provided. The package structure includes a die, a first encapsulant, a second encapsulant, a...
2019/0139846 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first...
2019/0139845 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer...
2019/0139844 METHOD FOR PROCESSING AN ELECTRICALLY INSULATING MATERIAL PROVIDING SAME WITH SELF-ADJUSTING ELECTRICAL FIELD...
A method for processing an electrically insulating protective material intended for covering at least one surface of an electrical component to be insulated,...
2019/0139843 SEMICONDUCTOR CHIP PACKAGE
This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for...
2019/0139842 SEMICONDUCTOR STRUCTURE
The present disclosure provides a semiconductor structure including a substrate, a first die vertically over the substrate, a second die vertically over the...
2019/0139841 SEMICONDUCTOR TEST STRUCTURE AND METHOD FOR FORMING THE SAME
A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed...
2019/0139840 WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS
A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut...
2019/0139839 SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER HAVING PROTRUDING BOTTOM PORTION AND METHOD FOR FORMING THE SAME
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack...
2019/0139838 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and...
2019/0139837 METHOD FOR MANUFACTURING MULTI-VOLTAGE DEVICES USING HIGH-K-METAL-GATE (HKMG) TECHNOLOGY
Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain...
2019/0139836 Source/Drain Features with an Etch Stop Layer
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region,...
2019/0139835 ELECTRONIC DEVICE BASED ON TWO-DIMENSIONAL SEMICONDUCTOR AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally...
2019/0139834 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region...
2019/0139833 VERTICAL FIELD EFFECT TRANSISTOR (FET) WITH CONTROLLABLE GATE LENGTH
A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on...
2019/0139832 FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a...
2019/0139831 SEMICONDUCTOR ARRANGEMENTS AND METHODS OF MANUFACTURING THE SAME
Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first...
2019/0139830 SELF-ALIGNED GATE ISOLATION
Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes...
2019/0139829 Wrap Around Silicide for FinFETs
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the...
2019/0139828 Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device...
2019/0139827 3D SEMICONDUCTOR DEVICE AND SYSTEM
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer,...
2019/0139826 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH RESISTIVE ELEMENT
Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first...
2019/0139825 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate...
2019/0139824 METHOD OF SELF-ALIGNED DOUBLE PATTERNING
A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and...
2019/0139823 METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING STRUCTURES
One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias...
2019/0139822 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first...
2019/0139821 ADVANCED BEOL INTERCONNECT ARCHITECTURE
Advanced dual damascene interconnects that exhibit controlled via resistance and, in some instances, controlled line resistance are provided. In one...
2019/0139820 ADVANCED BEOL INTERCONNECT ARCHITECTURE
Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a...
2019/0139819 SEMICONDUCTOR STRUCTURE WITH AIRGAP
A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a...
2019/0139818 HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an...
2019/0139817 Semiconductor Packaging Structure and Process
A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded...
2019/0139816 SEMICONDUCTOR STRUCTURE INCLUDING ISOLATIONS AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming...
2019/0139815 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first...
2019/0139814 SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURES WITH DIFFERENT THICKNESSES
A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The...
2019/0139813 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the...
2019/0139812 Multi-Barrier Deposition for Air Gap Formation
A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a...
2019/0139811 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region...
2019/0139810 APPARATUS AND SYSTEM FOR PREVENTING BACKSIDE PEELING DEFECTS ON SEMICONDUCTOR WAFERS
A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift...
2019/0139809 SUBSTRATE SUPPORTING AND TRANSFERRING APPARATUS, METHOD OF SUPPORTING AND TRANSFERRING SUBSTRATE, AND...
A substrate supporting and transferring apparatus and associated methods, the apparatus including a shuttle configured to move in a x-direction and a...
2019/0139808 APPARATUS AND METHODS FOR ISOLATING A REACTION CHAMBER FROM A LOADING CHAMBER RESULTING IN REDUCED CONTAMINATION
The present disclosure relates to a semiconductor processing apparatus having a reaction chamber which can include a baseplate having an opening; a moveable...
2019/0139807 APPARATUS AND METHODS FOR ISOLATING A REACTION CHAMBER FROM A LOADING CHAMBER RESULTING IN REDUCED CONTAMINATION
The present disclosure relates to a semiconductor processing apparatus having a reaction chamber which can include a baseplate having an opening; a moveable...
2019/0139806 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device according to the present invention includes at least the following four steps: (A) a step of preparing a...
2019/0139805 HEATER SYSTEM, CERAMIC HEATER, PLASMA TREATMENT DEVICE AND ADSORPTION DEVICE
A heater system may include a ceramic heater and a drive device. The ceramic heater may include a ceramic substrate and a resistance heating element. The...
2019/0139804 SUBSTRATE PROCESSING APPARATUS AND NOTIFICATION METHOD
A substrate processing apparatus disclosed herein is capable of communicating with an external control apparatus. The substrate processing apparatus includes:...
2019/0139803 SEMICONDUCTOR STOCKER SYSTEMS AND METHODS
In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV)...
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