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Patent # Description
2019/0138486 HOT UNPLUG PREDICTIONS BASED ON LATCH POSITIONS
An example peripheral device includes a module interface to receive power and data communication from a computing device. The peripheral device also includes...
2019/0138485 COMPUTING DEVICES WITH HOT SWAPPING PREDICTION CIRCUITS
An example computing device includes a module interface to communicate with a peripheral device. The computing device also includes a hot swapping prediction...
2019/0138484 CONTROL CIRCUIT
A method, control circuit and printing system to control data communications with a plurality of integrated circuits. The method comprises receiving a control...
2019/0138483 Controlling a Mode of Communication Between a Host Computer and a Detachable Peripheral Device
A technique includes communicating data between a host computer and a peripheral device. The peripheral device is docked to the host computer, and the...
2019/0138482 STORAGE DEVICE CARRIER ASSEMBLY
A computing system for housing a number of storage devices includes a number of device cages, and a backplane coupled to each of the device cages to...
2019/0138481 TECHNOLOGIES FOR PROVIDING DYNAMIC COMMUNICATION PATH MODIFICATION FOR ACCELERATOR DEVICE KERNELS
Technologies for providing dynamic communication path modification for accelerator device kernels include an accelerator device comprising circuitry to obtain...
2019/0138480 STORAGE SYSTEM AND CONTROL METHOD THEREFOR
According to an aspect of the present disclosure, SATA bridges in cascade connection and storage devices connected beyond the SATA bridges are identified. A...
2019/0138479 AGING TOLERANT SYSTEM DESIGN USING SILICON RESOURCE UTILIZATION
An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for...
2019/0138478 LOCATION-BASED ADDRESS ADAPTER AND SYSTEM
A location-based address adapter for use in a system to facilitate communication between a host computer and one peripheral device of a plurality of peripheral...
2019/0138477 MODULAR HUB
A modularized hub is adapted to be electrically connected to an upstream device, an AC power source and at least one downstream device that are located outside...
2019/0138476 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UNIT, AND MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
There are provided a universal asynchronous receiver/transmitter (UART) unit, and a memory controller and a memory system, which have the UART unit. A UART...
2019/0138475 KVM EXTENSION DEVICE SELF-CONTAINED WITHIN A VIDEO CONNECTOR
The present disclosure is directed to an apparatus for forming an interface for interfacing a remote access appliance ("RAC") to a target device ("TD") and...
2019/0138474 SYSTEM, METHOD, AND RECORDING MEDIUM FOR TOPOLOGY-AWARE PARALLEL REDUCTION IN AN ACCELERATOR
A topology-aware parallel reduction method, system, and recording medium including obtaining the GPU connection topology of each of the plurality of GPUs as a...
2019/0138473 SEMICONDUCTOR DEVICES INCLUDING COMMAND PRIORITY POLICY MANAGEMENT AND RELATED SYSTEMS
Provided is a semiconductor device and a semiconductor system. A semiconductor device can include a command priority policy manager circuit which generates...
2019/0138472 VALIDATION OF CORRECTNESS OF INTERRUPT TRIGGERS AND DELIVERY
In an approach to validation of correctness of interrupt triggers and delivery a computer allocates one or more flags of a gang of flags. The computer...
2019/0138471 HIGH PERFORMANCE COMPUTING NETWORK
The present invention relates to a method of processing data in a computer system, the method comprising the steps of: 1) allocating at least one processing...
2019/0138470 ASYMMETRIC LANES IN A POINT-TO-POINT INTERCONNECT
A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral...
2019/0138469 ELECTRONIC DEVICE AND METHOD FOR CONTROLLING SAME
Electronic devices according to various embodiments of the present invention comprise: a connector for communicating serial data to an external electronic...
2019/0138468 USING TRANSFER BUFFER TO HANDLE HOST READ COLLISIONS IN SSD
An embodiment of a semiconductor apparatus may include technology to detect a collision for a read request of an electronic storage device, and read data for...
2019/0138467 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document...
2019/0138466 REFLECTIVE MEMORY BRIDGE FOR EXTERNAL COMPUTING NODES
In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective...
2019/0138465 METHOD TO REDUCE WRITE RESPONSES TO IMPROVE BANDWIDTH AND EFFICIENCY
Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes system memory and one or...
2019/0138464 TECHNOLOGIES FOR PROVIDING I/O CHANNEL ABSTRACTION FOR ACCELERATOR DEVICE KERNELS
Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability...
2019/0138463 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM
[Object] To enable a user's feeling at the time of recording to be experienced by another user. [Solution] An information processing apparatus according to the...
2019/0138462 FIXED ETHERNET FRAME DESCRIPTOR
System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network...
2019/0138461 INFORMATION AND CONTROL VIA VOICE COMMUNICATIONS MODULE FOR WORK SURFACE POWER AND DATA UNITS
An electrical power and/or electronic data unit with voice communications capability includes a housing, a voice communications module, and an electrical power...
2019/0138460 HARDWARE INDEPENDENT PERIPHERAL CONTROL SYSTEM AND METHOD
A hardware independent peripheral control system and method are disclosed. The system comprises: a virtualised controller (20) executable by a processor (35)...
2019/0138459 In-Memory Distributed Cache
A method for an in-memory distributed cache includes receiving a write request from a client device to write a block of client data in random access memory...
2019/0138458 DATA PROCESSING SYSTEMS
When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an...
2019/0138457 UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY
Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein...
2019/0138456 PREDICTIVE MEMORY MANAGEMENT
A query for data stored in a database that includes a set of segments is received at a computer system. The set of segments are divided into a plurality of...
2019/0138455 MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME
Provided herein may be a memory controller and a method of operating the same. The memory controller controls a semiconductor memory device including a...
2019/0138454 MEMORY SYSTEM AND OPERATION METHOD THEREOF
A memory system includes a non-volatile memory device including a plurality of memory blocks; and a controller comprising a volatile memory and configured to:...
2019/0138453 COMPUTER MEMORY CONTENT MOVEMENT
In some examples, computer memory content movement may include ascertaining a request associated with content of computer memory. Based on a determination that...
2019/0138452 AUTONOMOUS PREFETCH ENGINE
A control circuit for controlling memory prefetch requests to system level cache (SLC). The control circuit includes a circuit identifying memory access...
2019/0138451 SYSTEMS AND METHODS FOR ADAPTIVE MULTIPATH PROBABILITY (AMP) PREFETCHER
Disclosed embodiments relate to systems and methods structured to predict and prefetch a cache access based on a delta pattern. In one example, a processor is...
2019/0138450 METHOD TO AVOID CACHE ACCESS CONFLICT BETWEEN LOAD AND FILL
According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in...
2019/0138449 COORDINATED CACHE MANAGEMENT POLICY FOR AN EXCLUSIVE CACHE HIERARCHY
Embodiments include a method and system for coordinating cache management for an exclusive cache hierarchy. The method and system may include managing, by a...
2019/0138448 READ-WITH-INVALIDATE MODIFIED DATA IN A CACHE LINE IN A CACHE MEMORY
Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received...
2019/0138447 CONTROLLER AND OPERATING METHOD THEREOF
A controller may include a memory suitable for caching write data and map data corresponding to the write data; and a processor suitable for flushing the...
2019/0138446 COMPRESSED PAGES HAVING DATA AND COMPRESSION METADATA
Examples include compressed pages having data and compression metadata. Some examples include receiving a write request containing write data, storing the...
2019/0138445 MAPPING TABLE UPDATING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
A mapping table updating method, a memory control circuit unit and a memory storage device. The method includes: receiving a first data corresponding to a...
2019/0138444 COMMON MCU SELF-IDENTIFICATION INFORMATION
Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central...
2019/0138443 TRIM SETTING DETERMINATION ON A MEMORY DEVICE
The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of...
2019/0138442 CONFIGURABLE TRIM SETTINGS ON A MEMORY DEVICE
The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring...
2019/0138441 AFFINITY DOMAIN-BASED GARBAGE COLLECTION
Affinity domain based garbage collection is facilitated for a non-uniform memory access (NUMA) computing environment. The affinity domain a memory region is...
2019/0138440 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system and an operating method thereof are provided. The memory system includes a nonvolatile memory device, and a memory controller, wherein the...
2019/0138439 MEMORY SYSTEM, CONTROLLER, METHOD OF OPERATING A CONTROLLER, AND METHOD OF OPERATING A MEMORY SYSTEM
In accordance with an embodiment, a controller may be provided. The controller may include a selection block configured to select cold data among write data....
2019/0138438 CONDITIONAL STACK FRAME ALLOCATION
A method for allocating memory includes an operation that determines whether a prototype of a callee function is within a scope of a caller. The caller is a...
2019/0138437 PERFORMANCE COUNTERS FOR COMPUTER MEMORY
In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The...
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