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Patent # Description
US-7,960,809 eFuse with partial SiGe layer and design structure therefor
A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe...
US-7,960,808 Reprogrammable fuse structure and method
A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in...
US-7,960,807 Ambient light detectors using conventional CMOS image sensor process
A CMOS light detector configured to detect specific wavelengths of light includes a first sensor and a second sensor. The first sensor includes CMOS photocells...
US-7,960,806 Sub-mount, light emitting diode package and manufacturing method thereof
A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are...
US-7,960,805 MEMS structure with suspended microstructure that includes dielectric layer sandwiched by plural metal layers...
An MEMS structure and a method of manufacturing the same are provided. The MEMS structure includes a substrate and at least one suspended microstructure located...
US-7,960,804 Latching zip-mode actuated mono wafer MEMS switch
A latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed....
US-7,960,803 Electronic device having a hafnium nitride and hafnium oxide film
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,960,802 Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low...
A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work...
US-7,960,801 Gate electrode stress control for finFET performance enhancement description
A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a ...
US-7,960,800 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using...
Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices...
US-7,960,799 Semiconductor device and method for manufacturing the same
A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a...
US-7,960,798 Structure and method to form multilayer embedded stressors
A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided....
US-7,960,797 Semiconductor devices including fine pitch arrays with staggered contacts
A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one...
US-7,960,796 Semiconductor device having element isolation region
An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration...
US-7,960,795 Partially and fully silicided gate stacks
Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided...
US-7,960,794 Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary ...
US-7,960,793 Semiconductor device
According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as...
US-7,960,792 Non-volatile memory with a stable threshold voltage on SOI substrate
A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The...
US-7,960,791 Dense pitch bulk FinFET process by selective EPI and etch
Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one...
US-7,960,790 Self-aligned planar double-gate transistor structure
A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal...
US-7,960,789 Integrated field-effect transistor comprising two control regions, use of said field-effect transistor and...
An integrated field-effect transistor is described in which a substrate region is surrounded by: two terminal regions (a source region and a drain region), two...
US-7,960,788 Replacing symmetric transistors with asymmetric transistors
A semiconductor structure includes a symmetric metal-oxide-semiconductor (MOS) transistor comprising a first and a second asymmetric MOS transistor. The first...
US-7,960,787 Configuration of trenched semiconductor power device to reduce masked process
A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates...
US-7,960,786 Breakdown voltages of ultra-high voltage devices by forming tunnels
A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate,...
US-7,960,785 Semiconductor integrated circuit devices
A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the...
US-7,960,784 Semiconductor structure and fabrication method thereof
A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width...
US-7,960,783 Devices containing permanent charge
An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity...
US-7,960,782 Nitride semiconductor device and method for producing nitride semiconductor device
A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a...
US-7,960,781 Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers....
US-7,960,780 Vertical-type semiconductor device
In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes...
US-7,960,779 Nonvolatile semiconductor memory and manufacturing method thereof
A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the...
US-7,960,778 Flash memory cell string
The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected...
US-7,960,777 Multi-valued mask ROM
A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first...
US-7,960,776 Transistor with floating gate and electret
A sensor includes a field effect transistor having a source, drain, a control gate and floating gate, wherein the floating gate has an extended portion...
US-7,960,775 Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof
The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of...
US-7,960,774 Memory devices including dielectric thin film and method of manufacturing the same
A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device...
US-7,960,773 Capacitor device and method for manufacturing the same
This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be...
US-7,960,772 Tuning capacitance to enhance FET stack voltage withstand
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected...
US-7,960,771 Semiconductor device comprising a switching element and memory element having an organic compound
A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer...
US-7,960,770 Nonvolatile memory element array with storing layer formed by resistance variable layers
A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from...
US-7,960,769 Solid-state imaging device and method for manufacturing same
In a CMOS image sensor, an N-type semiconductor layer is formed on a P-type semiconductor substrate. P-type semiconductor regions are formed in one part of the...
US-7,960,768 3D backside illuminated image sensor with multiplexed pixel structure
A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array...
US-7,960,767 System for programmable gate array with sensor array
The present invention provides providing a substrate, forming a sensor array on the substrate, forming a structured array of uncommitted logic surrounding the...
US-7,960,766 Light sensors with infrared suppression
Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are...
US-7,960,765 Method and apparatus for providing an integrated circuit having p and n doped gates
A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and...
US-7,960,764 Semiconductor device manufacturing method and semiconductor device
Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor...
US-7,960,763 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon...
US-7,960,762 Solid-state image sensing device including solid-state image sensor having a pillar-shaped semiconductor layer
It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving...
US-7,960,761 Semiconductor device having a recess channel transistor
The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region...
US-7,960,760 Electrically programmable fuse
A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region....
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