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| Patent # | Description |
|---|---|
| US-7,962,715 |
Memory controller for non-homogeneous memory system A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of... |
| US-7,962,714 |
System and method for performing auxiliary storage operations Systems and methods for protecting data in a tiered storage system are provided. The storage system comprises a management server, a media management component... |
| US-7,962,713 |
Memory device having secure non-volatile locking functionality A device and method is provided for maintaining, upon unlocking of a memory, the lock status of the memory prior to the memory being unlocked and recreating the... |
| US-7,962,712 |
Method for controlling storage device controller, storage device
controller, and program Disclosed herein is a method for controlling a storage device controller connected to a storage device provided with a plurality of storage volumes for storing... |
| US-7,962,711 |
Pre-caching files from removable device to expedite perceived download
performance A method and a processing device may be provided for detecting a device newly connected to the processing device. The processing device may copy files from the... |
| US-7,962,710 |
Techniques for creating checkpoints Techniques for creating checkpoints are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for creating file system... |
| US-7,962,709 |
Network redirector systems and methods for performing data replication Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application... |
| US-7,962,708 |
Resolving retention policy conflicts Resolving retention policy conflicts is disclosed. An indication is received that two or more retention policies apply to an item of content. A merged retention... |
| US-7,962,707 |
Apparatus and method for deterministic garbage collection of a heap memory A method includes executing an application in an execution environment. The application is allocated a plurality of memory blocks in a memory during execution.... |
| US-7,962,706 |
Methods and systems for improving read performance in data de-duplication
storage The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides... |
| US-7,962,705 |
System and method for providing a virtual memory architecture narrower and
deeper than a physical memory... Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location... |
| US-7,962,704 |
Storage system of storage hierarchy devices and a method of controlling
storage hierarchy devices based on a... A storage control apparatus according to the present invention includes a plurality of connecting units connected to one or more host computers and one or more... |
| US-7,962,703 |
Techniques for improving dirty page logging Techniques for improving dirty page logging are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for memory logging... |
| US-7,962,702 |
Multiple independent levels of security (MILS) certifiable RAM paging
system The present invention is directed to an integrated circuit, a method and a system for executing a sequence of instruction loaded from an external storage... |
| US-7,962,701 |
Recording meduim playback apparatus In one aspect of the invention, text data recorded on a CD conforming to the CD-TEXT format is displayed using a minimum amount of memory. Storage capacity to... |
| US-7,962,700 |
Systems and methods for reducing latency for accessing compressed memory
using stratified compressed memory... Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory... |
| US-7,962,699 |
Concurrent execution of critical sections by eliding ownership of locks One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During... |
| US-7,962,698 |
Deterministic collision detection An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving... |
| US-7,962,697 |
Contention detection A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute... |
| US-7,962,696 |
System and method for updating owner predictors Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that... |
| US-7,962,695 |
Method and system for integrating SRAM and DRAM architecture in set
associative cache A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class,... |
| US-7,962,694 |
Partial way hint line replacement algorithm for a snoop filter In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors,... |
| US-7,962,693 |
Cache management system providing improved page latching methodology A cache management system providing improved page latching methodology. A method providing access to data in a multi-threaded computing system comprises:... |
| US-7,962,692 |
Method and system for managing performance data The present invention is directed to a method and system for managing performance data. In accordance with a particular embodiment of the present invention,... |
| US-7,962,691 |
Information processing apparatus and computer usable medium therefor An information processing apparatus capable of executing at least one information processing operation is provided. The information processing apparatus... |
| US-7,962,690 |
Apparatus and method to access data in a raid array A method to access a data in a RAID array comprising a plurality of data storage media, wherein information is written to said plurality of data storage media... |
| US-7,962,689 |
System and method for performing transactional processing in a striped
volume set A storage system architecture ensures transactional processing of operations directed to one or more data containers stored on a plurality of volumes... |
| US-7,962,688 |
Semiconductor storage device with nonvolatile and volatile memories,
method of controlling the same, controller... A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller... |
| US-7,962,687 |
Flash memory allocation for improved performance and endurance A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller... |
| US-7,962,686 |
Efficient preservation of the ordering of write data within a subsystem
that does not otherwise guarantee... A technique for efficiently preserving the ordering of data being written to a nonvolatile memory through a subsystem of a network storage system in the event... |
| US-7,962,685 |
Portable data storage device incorporating multiple flash memory units A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host... |
| US-7,962,684 |
Overlay management in a flash memory storage device The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically... |
| US-7,962,683 |
Flash memory, and method for operating a flash memory A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data... |
| US-7,962,682 |
Multi-module simultaneous program, erase test, and performance method for
flash memory Methods and apparatus for accessing modules on a flash memory package concurrently during testing are disclosed. According to one aspect of the present... |
| US-7,962,681 |
System and method of conditional control of latch circuit devices A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a... |
| US-7,962,680 |
Image forming apparatus and connection notifying method An image forming apparatus includes an operating unit, a controller, and a transmission line that connects the operating unit to the controller. The operating... |
| US-7,962,679 |
Interrupt balancing for multi-core and power A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a... |
| US-7,962,678 |
Bus arbitration apparatus and method A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so... |
| US-7,962,677 |
Bus access moderation system A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get... |
| US-7,962,676 |
Debugging multi-port bridge system conforming to serial advanced
technology attachment (SATA) or serial... An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or... |
| US-7,962,675 |
Method and system for communicating with a host bus adapter Method and system for a storage area network is provided. The method includes sending a command from a management application executed in a first host system... |
| US-7,962,674 |
Buffer management device, buffer management method, and integrated circuit
for buffer management A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a... |
| US-7,962,673 |
Method and apparatus for accessing a data bus to transfer data over the
data bus A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting... |
| US-7,962,672 |
Techniques for data storage configuration Described are techniques for storage configuration. Defined are one or more initiator groups each including one or more initiator ports, one or more target... |
| US-7,962,671 |
Storage apparatus and method of updating control information in storage
apparatus A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store... |
| US-7,962,670 |
Pin multiplexing A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A... |
| US-7,962,669 |
Memory controller and memory control method A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception... |
| US-7,962,668 |
USB audio controller A USB audio controller includes a USB interface unit, an audio interface unit, a storage interface unit, and a processing unit. The USB interface unit is used... |
| US-7,962,667 |
System core for transferring data between an external device and memory Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are... |
| US-7,962,666 |
Transfer apparatus, transfer system, program, and transfer method A transfer apparatus includes a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer... |
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