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| Patent # | Description |
|---|---|
| US-7,969,002 |
Integrated circuit packages incorporating an inductor and methods Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a... |
| US-7,969,001 |
Method and system for intra-chip waveguide communication Methods and systems for intra-chip waveguide communication are disclosed and may include configuring one or more waveguides in an integrated circuit and... |
| US-7,969,000 |
Semiconductor device A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor... |
| US-7,968,999 |
Process of grounding heat spreader/stiffener to a flip chip package using
solder and film adhesive A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a... |
| US-7,968,998 |
Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat
semiconductor package A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated... |
| US-7,968,997 |
Semiconductor device A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals.... |
| US-7,968,996 |
Integrated circuit package system with supported stacked die An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the... |
| US-7,968,995 |
Integrated circuit packaging system with package-on-package and method of
manufacture thereof A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base... |
| US-7,968,994 |
Memory modules and systems including the same Provided is a memory module. The memory module may include a mounting substrate including a plurality of first substrate pads disposed on a top surface of the... |
| US-7,968,993 |
Stacked semiconductor device and semiconductor memory device A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first... |
| US-7,968,992 |
Multi-chip package structure and method of fabricating the same A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first... |
| US-7,968,991 |
Stacked package module and board having exposed ends A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein... |
| US-7,968,990 |
Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the... |
| US-7,968,989 |
Multi-package slot array A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a... |
| US-7,968,988 |
Power semiconductor module having a thermally conductive base plate on
which at least four substrates are... The power semiconductor module (1) has a heat-conducting base plate (11) on which at least three substrates (2, 3, 4, 5, 6, 7) are placed, each substrate... |
| US-7,968,987 |
Carbon dioxide gettering for a chip module assembly A chip module assembly includes a CO.sub.2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed... |
| US-7,968,986 |
Lid structure for microdevice and method of manufacture A system and a method are described for forming features at the bottom of a cavity in a substrate. Embodiments of the systems and methods provide an infrared... |
| US-7,968,984 |
Universal pad arrangement for surface mounted semiconductor devices An apparatus for coupling a plurality of surface mounted semiconductor device packages to a circuit board is provided. Each package including a semiconductor... |
| US-7,968,983 |
Semiconductor device Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor... |
| US-7,968,982 |
Thermal enhanced upper and dual heat sink exposed molded leadless package A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the... |
| US-7,968,981 |
Inline integrated circuit system An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an... |
| US-7,968,980 |
Support member for mounting a semiconductor device, conductive materials,
and its manufacturing method A semiconductor device comprises a support member having a pair of first conductive materials and a pair of second conductive materials on an insulating... |
| US-7,968,979 |
Integrated circuit package system with conformal shielding and method of
manufacture thereof An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads,... |
| US-7,968,978 |
Microwave integrated circuit package and method for forming such package A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and... |
| US-7,968,977 |
Dicing film having shrinkage release film and method of manufacturing
semiconductor package using the same The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a... |
| US-7,968,976 |
Guard ring extension to prevent reliability failures An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over... |
| US-7,968,975 |
Metal wiring structure for integration with through substrate vias An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level... |
| US-7,968,974 |
Scribe seal connection A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical... |
| US-7,968,973 |
Semiconductor for macro and micro frequency tuning, and antenna and
frequency tuning circuit having the... A semiconductor element for macro and micro frequency tuning, and an antenna and a frequency tuning circuit having the semiconductor element, are provided. The... |
| US-7,968,972 |
High-frequency bipolar transistor and method for the production thereof A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a... |
| US-7,968,971 |
Thin-body bipolar device A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the... |
| US-7,968,970 |
Semiconductor device, method for manufacturing semiconductor device, and
power amplifier element A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial... |
| US-7,968,969 |
Electrical components for microelectronic devices Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing... |
| US-7,968,968 |
Inductor utilizing pad metal layer An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the... |
| US-7,968,967 |
One-time-programmable anti-fuse formed using damascene process A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power... |
| US-7,968,966 |
Semiconductor device with fuse and a method of manufacturing the same In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer... |
| US-7,968,965 |
Semiconductor device and method for fabricating the same Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device,... |
| US-7,968,964 |
High density photodiodes The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC)... |
| US-7,968,963 |
Photodiode array and image pickup device using the same A photodiode array with reduced optical crosstalk and an image pickup device using it are provided. The photodiode array 10 according to the present invention... |
| US-7,968,962 |
Semiconductor fabrication method and system A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a... |
| US-7,968,961 |
Solid-state image pickup device and method for manufacturing the same A solid-state image pickup device which includes a solid-state image pickup chip, a transparent plate disposed to face a light-receiving surface of the... |
| US-7,968,960 |
Methods of forming strained semiconductor channels In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region... |
| US-7,968,959 |
Methods and systems of thick semiconductor drift detector fabrication Gray-tone lithography technology is used in combination with a reactive plasma etching operation in the fabrication method and system of a thick semiconductor... |
| US-7,968,958 |
Semiconductor device and manufacturing method of the same A semiconductor device includes: a sensor element having a plate shape with a surface and including a sensor structure disposed in a surface portion of the... |
| US-7,968,957 |
Transistor gate electrode having conductor material layer Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having... |
| US-7,968,956 |
Semiconductor device A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate... |
| US-7,968,955 |
Gate in semiconductor device and method of fabricating the same A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive... |
| US-7,968,954 |
Intermediate semiconductor device having nitrogen concentration profile A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is... |
| US-7,968,953 |
Semiconductor device including schottky barrier diode and method of
manufacturing the same A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second... |
| US-7,968,952 |
Stressed barrier plug slot contact structure for transistor performance
enhancement A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact... |
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