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Data reading module and method for reading optical disc
Disclosed is a data reading module for reading an optical disc with data regions and undesired regions, wherein at least one of the undesired regions is located...
Music data transfer method, information processing apparatus and
information recording/playback system
One embodiment of invention is useful when updating data of a database which is configured to take in data through a network, has a part to be updated, and...
Performing error-free access operation on multi-layered disc
A method of reproducing information recorded on an optical disc having a plurality of recording layers inclusive of a first recording layer and a second...
Electronic device with an alarm clock function and method of controlling
An electronic device with an alarm clock function includes a storage unit storing at least one icon; a display unit including a plurality of display areas; an...
A seismograph system includes a seismometer, a positioning unit, a transmitter, a remote processing device. The seismometer includes a micro electromechanical...
System and method for implementing non-lethal chemical warfare against
A system and method for implementing non-lethal chemical warfare against rampage shooters. A sound detection module detects a sound of a gunshot from at least...
Method and system for real-time automated change detection and
classification for images
A computer based system and method for real-time display of co-registered historical and current side scan sonar imagery during a side scan sonar survey....
Deployment and retrieval method for shallow water ocean bottom
The deployment method for deploying seismic data acquisition units into shallow water from the deck of a vessel provides for deploying a cable into the water....
Selective edge phase mixing
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and...
Internal write/read pulse generating circuit of a semiconductor memory
A control clock generating unit outputs a clock as a control clock when a column address strobe pulse is input and fixes the control clock to a specific level...
Circuit and method for controlling DRAM column-command address
The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a...
Semiconductor memory device that includes an address coding method for a
multi-word line test
Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding...
Integrated circuit including a memory module having a plurality of memory
An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory...
State of health monitored flash backed dram module
A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a...
Energy efficient memory access technique for single ended bit cells
A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality...
Dynamic random access memory (DRAM) refresh
A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and...
Semiconductor apparatuses and methods of operating the same
A method of operating a semiconductor device is provided including applying a constant source voltage to a source line.
Semiconductor device having single-ended sensing amplifier
A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold...
Hybrid sense amplifier and method, and memory device using same
Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit....
Semiconductor memory device
A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection...
Write driver circuit of PRAM
A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver...
Semiconductor memory device and control method
A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each...
Refresh characteristic testing circuit and method for testing refresh
using the same
A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the...
Memory compiler redundancy
An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded...
Read-leveling implementations for DDR3 applications on an FPGA
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming...
Delay locked loop circuit of semiconductor device
A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency....
Clock signal generating circuit and data output apparatus using the same
A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by...
Postamble timing for DDR memories
Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A...
Data strobe signal noise protection apparatus and semiconductor integrated
A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of...
Write strobe generation for a memory interface controller
A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe...
Multiple threshold voltage register file cell
A memory circuit may include a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of...
Method of operating semiconductor devices
A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to...
Nonvolatile semiconductor memory and method for testing the same
A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a...
Method, apparatus and system for transmitting data in semiconductor device
Provided is a method of inverting data that is to be transmitted and transmitting the data in a semiconductor device. The method includes inverting bits of data...
Semiconductor memory device with optimum refresh cycle according to
A semiconductor memory device, which performs a refresh operation, includes: a temperature sensing unit for measuring temperature and for generating a...
Methods of operating memory devices including different sets of logical
Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second...
Communication device and method for erasing data from a communication
A communication device and method for erasing data include setting erasing parameters and initializing the erasing parameters, erasing data in a target data...
Sub volt flash memory system
Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The...
Memory device having improved programming operation
Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and...
Program method of flash memory device
A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are...
Method of programming nonvolatile memory device
In a method of programming a nonvolatile memory device, when a program is performed, a program voltage is applied to a first word line selected for the program....
Method of programming and sensing memory cells using transverse channels
and devices employing same
A first channel in the substrate underlying a trap gate is biased to cause trapping of holes or electrons in the trap gate and thereby program the memory device...
Setting memory controller driver to memory device termination value in a
A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the...
Flash memory system having cross-coupling compensation during read
A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an...
Multi-bit-per-cell flash memory device with non-bijective mapping
To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to...
Least significant bit page recovery method used in multi-level cell flash
A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device includes setting first through n.sup.th LSB page groups...
Post-facto correction for cross coupling in a flash memory
A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting...
Memory with weighted multi-page read
A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation....
Integrated circuits to control access to multiple layers of memory
Circuits to control access to memory; for example, third dimension memory are provided. An integrated circuit (IC) may be configured to control access to memory...
Immunity of phase change material to disturb in the amorphous phase
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset...