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Patent # Description
US-7,989,351 Method for manufacturing a wiring over a substrate
A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate...
US-7,989,350 Method for fabricating semiconductor device with recess gate
A method for fabricating a semiconductor device includes forming a structure including a sacrificial layer and a hard mask over a substrate, performing a plasma...
US-7,989,349 Methods of manufacturing nanotubes having controlled characteristics
A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further,...
US-7,989,348 Polishing method and polishing apparatus
A polishing method that carries out a multi-step polishing process with improved polishing conditions (polishing recipe) while omitting measurement of the...
US-7,989,347 Process for filling recessed features in a dielectric substrate
A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a...
US-7,989,346 Surface treatment of silicon
A method of forming a resist pattern on a silicon semiconductor substrate having an anti-reflective layer thereon is described. The method includes the steps of...
US-7,989,345 Methods of forming blind wafer interconnects, and related structures and assemblies
Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface...
US-7,989,344 Method for forming a nickelsilicide FUSI gate
Ni.sub.3Si.sub.2 FUSI gates can be formed inter alia by further reaction of NiSi/Ni.sub.2Si gate stacks. Ni.sub.3Si.sub.2 behaves similarly to NiSi in terms of...
US-7,989,343 Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features
We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a...
US-7,989,342 Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with...
The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two...
US-7,989,341 Dual damascence copper process using a selected mask
A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two...
US-7,989,340 Methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive...
The invention included to methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts. In one...
US-7,989,339 Vapor deposition processes for tantalum carbide nitride materials
Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition...
US-7,989,338 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted...
US-7,989,337 Implementing vertical airgap structures between chip metal layers
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of...
US-7,989,336 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of...
A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a...
US-7,989,335 Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including...
In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed...
US-7,989,334 Method of manufacturing semiconductor device
In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is...
US-7,989,333 Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers
Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the...
US-7,989,332 Thin film transistor, display device having thin film transistor, and method for manufacturing the same
A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film...
US-7,989,331 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an...
US-7,989,330 Dry etching method
After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing...
US-7,989,329 Removal of surface dopants from a substrate
A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant...
US-7,989,328 Resistive memory array using P-I-N diode select device and methods of fabrication thereof
An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such...
US-7,989,327 Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step
A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si.sub.1-xGe.sub.x layer is formed on a superficial layer of...
US-7,989,326 Thin film transistor and method of fabricating the same
A thin film transistor and method of fabricating the same are provided. The thin film transistor includes: a metal catalyst layer formed on a substrate, and a...
US-7,989,325 Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor
A crystalline semiconductor film is manufactured by a first step in which a crystalline semiconductor film is formed on and in contact with an insulating film...
US-7,989,324 Method for manufacturing silicon on sapphire wafer
The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride...
US-7,989,323 Doping method
Methods of doping a III-V compound semiconductor film are disclosed.
US-7,989,322 Methods of forming transistors
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,989,321 Semiconductor device gate structure including a gettering layer
A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate...
US-7,989,320 Die bonding
A die bonding method and apparatus by which a wafer substrate 11 adhered to a carrier tape 13 by an adhesive layer 12 is laser machined through the wafer...
US-7,989,319 Semiconductor die singulation method
In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.
US-7,989,318 Method for stacking semiconductor dies
A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a...
US-7,989,317 Manufacturing method of semiconductor device
To provide a manufacturing method of a semiconductor device in which manufacturing cost can be reduced, and a manufacturing method of a semiconductor device...
US-7,989,316 Method of manufacturing semiconductor device
To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first...
US-7,989,315 Method for manufacturing semiconductor device
When printing is performed on a base substrate with a laser after a single crystal silicon layer is transferred to the base substrate, there are problems such...
US-7,989,314 Method of manufacturing a flexible device and method of manufacturing a flexible display
Provided are a method of separating a metal layer and an organic light emitting diode. A method of manufacturing a flexible device and a method of manufacturing...
US-7,989,313 Method and apparatus for creating RFID devices
A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first...
US-7,989,312 Double-sided integrated circuit chips
A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having...
US-7,989,311 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,989,310 Filling of insulation trenches using CMOS standard processes for creating dielectrically insulated areas on a...
Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO.sub.2 is formed...
US-7,989,309 Method of improving a shallow trench isolation gapfill process
A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate...
US-7,989,308 Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher...
The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by...
US-7,989,307 Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and...
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography...
US-7,989,306 Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried...
US-7,989,305 Method for manufacturing SOI substrate using cluster ion
A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by...
US-7,989,304 Method for transferring semiconductor element, method for manufacturing semiconductor device, and semiconductor...
A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting...
US-7,989,303 Method of creating an alignment mark on a substrate and substrate
In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line...
US-7,989,302 Methods of forming a hyper-abrupt P-N junction and design structures for an integrated circuit
Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The...
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