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| Patent # | Description |
|---|---|
| US-7,989,301 |
Semiconductor device with bipolar transistor and method of fabricating the
same Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor... |
| US-7,989,300 |
Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate... |
| US-7,989,299 |
Semiconductor device, method of manufacturing the same, and method of
evaluating semiconductor device A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this... |
| US-7,989,298 |
Transistor having V-shaped embedded stressor A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a... |
| US-7,989,297 |
Asymmetric epitaxy and application thereof The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor... |
| US-7,989,296 |
Semiconductor device and method of manufacturing same A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate,... |
| US-7,989,295 |
Method of manufacturing semiconductor device A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a... |
| US-7,989,294 |
Vertical field-effect transistor A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A "buried"... |
| US-7,989,293 |
Trench device structure and fabrication A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A... |
| US-7,989,292 |
Method of fabricating a semiconductor device with a channel formed in a
vertical direction In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar... |
| US-7,989,291 |
Anisotropic stress generation by stress-generating liners having a
sublithographic width A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A ... |
| US-7,989,290 |
Methods for forming rhodium-based charge traps and apparatus including
rhodium-based charge traps Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic... |
| US-7,989,289 |
Floating gate structures Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the... |
| US-7,989,288 |
Transistor constructions and processing methods A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second... |
| US-7,989,287 |
Method for fabricating storage node electrode in semiconductor device A method for fabricating a storage node electrode in a semiconductor device includes: performing a primary high density plasma (HDP) process to form a first HDP... |
| US-7,989,286 |
Electronic devices using carbon nanotubes having vertical structure and
the manufacturing method thereof Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same. The method of manufacturing an... |
| US-7,989,285 |
Method of forming a film containing dysprosium oxide and hafnium oxide
using atomic layer deposition The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a... |
| US-7,989,284 |
DRAM cell transistor device and method A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The... |
| US-7,989,283 |
Manufacturing method of semiconductor device A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric... |
| US-7,989,282 |
Structure and method for latchup improvement using through wafer via
latchup guard ring A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up... |
| US-7,989,281 |
Method for manufacturing dual gate in semiconductor device Provided is a method for manufacturing a dual gate in a semiconductor device. The method includes forming a gate insulating layer and a gate conductive layer on... |
| US-7,989,280 |
Dielectric interface for group III-V semiconductor device A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region. |
| US-7,989,279 |
Method of fabricating semiconductor device A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided.... |
| US-7,989,278 |
Compound semiconductor device and method for fabricating the same The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN... |
| US-7,989,277 |
Integrated structure with transistors and Schottky diodes and process for
fabricating the same A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting... |
| US-7,989,275 |
Thin film transistor, manufacturing method thereof, display device, and
manufacturing method thereof A light-blocking layer is formed using a first resist mask, and a base film is formed over the light-blocking layer. A first conductive film, a first insulating... |
| US-7,989,274 |
Display device having oxide thin film transistor and fabrication method
thereof A display device including an oxide thin film transistor (TFT) is disclosed. A nitride-based gate insulating layer of a gate pad area is etched when an oxide... |
| US-7,989,273 |
Semiconductor substrate and manufacturing method of semiconductor device To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of... |
| US-7,989,272 |
Composition of carbon nitride, thin film transistor with the composition
of carbon nitride, display device with... A conventional composition of carbon nitride has a deposition method and properties limited. In the case of using the composition of carbon nitride as a... |
| US-7,989,271 |
Method for fabricating an LCD device A method for fabricating an LCD device is disclosed, in which a reliable thin film pattern is formed as process deviation is minimized. The method includes... |
| US-7,989,270 |
Semiconductor device and method of forming three-dimensional vertically
oriented integrated capacitors A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the... |
| US-7,989,269 |
Semiconductor package with penetrable encapsulant joining semiconductor
die and method thereof A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and... |
| US-7,989,268 |
Small form factor molded memory card and a method thereof A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the... |
| US-7,989,267 |
Manufacturing method of semiconductor device and manufacturing method of
lead frame Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding... |
| US-7,989,266 |
Methods for separating individual semiconductor devices from a carrier A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be... |
| US-7,989,265 |
Process for making a semiconductor system having devices that have
contacts on top and bottom surfaces of each... Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical... |
| US-7,989,264 |
Warpage resistant semiconductor package and method for manufacturing the
same A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a... |
| US-7,989,263 |
Method for manufacturing a micromechanical chip and a component having a
chip of this type In a method for manufacturing a micromechanical chip, a sacrificial layer and an epitaxy layer are initially applied to a semiconductor substrate to produce a... |
| US-7,989,262 |
Method of sealing a cavity Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material... |
| US-7,989,261 |
Fabricating a gallium nitride device with a diamond layer In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate... |
| US-7,989,260 |
Method of selectively forming atomically flat plane on diamond surface,
diamond substrate produced by the... The present invention provides a method of selectively forming a flat plane on an atomic level on a diamond (001), (110) or (111) surface. A method of... |
| US-7,989,259 |
Methods of manufacturing phase-changeable memory devices including upper
and lower electrodes A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an... |
| US-7,989,258 |
Apatite-containing film having photocatalytic activity and a process for
producing it An apatite-containing film having photocatalytic activity is produced by a process comprising the steps of preparing a liquid mixture comprising a Ca-containing... |
| US-7,989,257 |
Polysilazane, method of synthesizing polysilazane, composition for
manufacturing semiconductor device, and... Disclosed are polysilazane, a method of synthesizing the polysilazane, a composition for manufacturing a semiconductor device, and a method of manufacturing a... |
| US-7,989,256 |
Method for manufacturing CIS-based thin film solar cell In order to manufacture a CIS-based thin film solar cell that can achieve high photoelectric conversion efficiency by adding an alkali element to a light... |
| US-7,989,255 |
Optical device A method of forming an optical device comprising the steps of: providing a substrate comprising a first electrode capable of injecting or accepting charge... |
| US-7,989,254 |
Method for fabricating color filter using surface plasmon and method for
fabricating liquid crystal display device Discussed are methods for fabricating a color filter using a surface plasmon and a liquid crystal display (LCD) device capable of enhancing a transmittance... |
| US-7,989,253 |
Method of forming mask for lithography, method of forming mask data for
lithography, method of manufacturing... A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals... |
| US-7,989,252 |
Method for fabricating pixel cell of CMOS image sensor The present invention provides a method for fabricating a pixel cell of CMOS image sensor, comprising: preparing a semiconductor substrate divided into region I... |
| US-7,989,251 |
Variable resistance memory device having reduced bottom contact area and
method of forming the same A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom... |
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