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Patent # Description
US-7,995,409 Memory with independent access and precharge
Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a...
US-7,995,408 Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage...
A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad...
US-7,995,407 Semiconductor memory device and control method thereof
A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second...
US-7,995,406 Data writing apparatus and method for semiconductor integrated circuit
A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same...
US-7,995,405 Semiconductor memory device having a sense amplifier circuit with decreased offset
A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit...
US-7,995,404 Semiconductor IC device and data output method of the same
A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a...
US-7,995,403 Semiconductor integrated circuit with data bus inversion function
A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets,...
US-7,995,402 Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a...
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
US-7,995,401 Non-volatile semiconductor memory with page erase
In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural...
US-7,995,400 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative...
US-7,995,399 NAND memory device and programming methods
A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge...
US-7,995,398 Structures and methods for reading out non-volatile memories
Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier...
US-7,995,397 Power supply tracking single ended sensing scheme for SONOS memories
A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense...
US-7,995,396 Methods of operating memory devices
Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected...
US-7,995,395 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a...
US-7,995,394 Program voltage compensation with word line bias change to suppress charge trapping in memory
Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower...
US-7,995,393 Flash memory device and system including the same
The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a...
US-7,995,392 Semiconductor memory device capable of shortening erase time
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control...
US-7,995,391 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,995,390 NAND flash memory array with cut-off gate line and methods for operating and fabricating the same
A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a...
US-7,995,389 Multi-level nonvolatile semiconductor memory
A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a...
US-7,995,388 Data storage using modified voltages
A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with...
US-7,995,387 System and method to read data subject to a disturb condition
Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory....
US-7,995,386 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce...
Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory...
US-7,995,385 Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing
A system comprising a program component that programs one or more non-volatile memory ("NVM") cells of an array of pairs of NVM cells using FN tunneling, an...
US-7,995,384 Electrically isolated gated diode nonvolatile memory
A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are...
US-7,995,383 Magnetic tunnel junction cell adapted to store multiple digital values
A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also...
US-7,995,382 Information recording and reproducing apparatus
An information recording and reproducing apparatus, includes: a recording layer including a first layer including a first compound, the first compound being a...
US-7,995,381 Method of programming resistivity changing memory
A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in...
US-7,995,380 Negative differential resistance pull up element for DRAM
A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is...
US-7,995,379 Semiconductor memory device
A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a...
US-7,995,378 MRAM device with shared source line
In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated...
US-7,995,377 Semiconductor memory device
An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing...
US-7,995,376 Semiconductor storage device and manufacturing method thereof
A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first...
US-7,995,375 Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable...
US-7,995,374 Semiconductor memory device, method of manufacturing the same, and method of screening the same
A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a...
US-7,995,373 Semiconductor memory device and information processing system
A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each...
US-7,995,372 Resistance change memory device with stabilizing circuit coupled in series with selected resistance change...
A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable...
US-7,995,371 Threshold device for a memory array
A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different...
US-7,995,370 Semiconductor memory device and electronic apparatus
A ferroelectric memory includes a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells. The plurality of dummy...
US-7,995,369 Semiconductor memory device
This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit...
US-7,995,368 Memory cell architecture
Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring...
US-7,995,367 Circuit arrangement comprising a non-volatile memory cell and method
The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3)...
US-7,995,366 Homogenous cell array
A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to...
US-7,995,365 Method and apparatuses for managing double data rate in non-volatile memory
Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and...
US-7,995,364 DC/DC converter circuit and controller thereof
The present invention uses a multi-phase oscillator or a mono-stable circuit in order to charge the output instantly or within an acceptable time period when a...
US-7,995,363 DC-DC converter
A DC-DC converter includes a charge pump unit and a clock pulse generator unit. The charge pump unit precharges a boost node in response to a precharge clock...
US-7,995,362 High voltage full bridge circuit and method for operating the same
A circuit apparatus for providing an AC voltage to a load. The apparatus may include: a first, second, third and fourth switch, wherein the first switch is...
US-7,995,361 Circuit for output voltage error detect and feedback in SMPS
The present invention relates to an error information detection circuit and an error feedback circuit, which detect the error of an output voltage from a...
US-7,995,360 Power system with shared clamp reset
A power supply includes a first power converter, a second power converter, and a clamp reset circuit. The clamp reset circuit is electrically coupled to other...
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