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Patent # Description
US-7,994,055 Method of manufacturing semiconductor apparatus, and semiconductor apparatus
A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an...
US-7,994,054 Semiconductor device having oxidized metal film and manufacture method of the same
A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that...
US-7,994,053 Patterning method of metal oxide thin film using nanoimprinting, and manufacturing method of light emitting diode
A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a ...
US-7,994,052 High-density patterning
Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of...
US-7,994,051 Implantation method for reducing threshold voltage for high-K metal gate device
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor...
US-7,994,050 Method for forming dual damascene pattern
A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the...
US-7,994,049 Manufacturing method of semiconductor device including filling a connecting hole with metal film
The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film...
US-7,994,048 Method of manufacturing a through electrode
A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a...
US-7,994,047 Integrated circuit contact system
An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the...
US-7,994,046 Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the...
A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the...
US-7,994,045 Bumped chip package fabrication method and structure
A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer...
US-7,994,044 Semiconductor chip with contoured solder structure opening
Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is...
US-7,994,043 Lead free alloy bump structure and fabrication method
A method includes forming a patterned resist layer comprising a resist layer opening overlying a bond pad of a substrate. The resist layer opening is at least...
US-7,994,042 Techniques for impeding reverse engineering
Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method...
US-7,994,041 Method of manufacturing stacked semiconductor package using improved technique of forming through via
A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical...
US-7,994,040 Semiconductor device and fabrication thereof
A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon...
US-7,994,039 Method of fabricating semiconductor device
A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor...
US-7,994,038 Method to reduce MOL damage on NiSi
Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include...
US-7,994,037 Gate dielectrics of different thickness in PMOS and NMOS transistors
By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as...
US-7,994,036 Semiconductor device and fabrication method for the same
The semiconductor device includes a first transistor and a second transistor formed in a semiconductor substrate. The first transistor includes: a first gate...
US-7,994,035 Semiconductor device fabricating method including thermal oxidation of a substrate, forming a second oxide, and...
There is provided a method of fabricating a semiconductor device in which a gate electrode is formed on an oxide film, which is formed by thermal oxidation on a...
US-7,994,034 Temperature and pressure control methods to fill features with programmable resistance and switching devices
A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a...
US-7,994,033 Semiconductor apparatus and manufacturing method thereof
The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the...
US-7,994,032 Method of making deep junction for electrical crosstalk reduction of an image sensor
The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a...
US-7,994,031 Method of manufacturing CMOS devices by the implantation of N- and P-type cluster ions
A method of manufacturing a semiconductor device is further described, comprising the steps of providing a supply of dopant atoms or molecules into an...
US-7,994,030 Method for manufacturing antenna and method for manufacturing semiconductor device
The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid...
US-7,994,029 Method for patterning crystalline indium tin oxide using femtosecond laser
A method for patterning crystalline indium tin oxide (ITO) using femtosecond laser is disclosed, which comprises steps of: (a) providing a substrate with an...
US-7,994,028 Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and...
A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor...
US-7,994,027 Microwave heating for semiconductor nanostructure fabrication
The present invention grows nanostructures using a microwave heating-based sublimation-sandwich SiC polytype growth method comprising: creating a sandwich cell...
US-7,994,026 Plasma dicing apparatus and method of manufacturing semiconductor chips
A plasma dicing apparatus in which a semiconductor wafer with a protective sheet stuck thereonto covering the entire circuit-forming surface and with an...
US-7,994,025 Wafer processing method without occurrence of damage to device area
A wafer processing method of processing a wafer having on a front surface a device area where a plurality of devices are formed by being sectioned by...
US-7,994,024 Object cutting method
An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape 23 is electrically charged in a...
US-7,994,023 Manufacturing methods of SOI substrate and semiconductor device
A manufacturing method of an SOI substrate and a manufacturing method of a semiconductor device are provided. When a large-area single crystalline semiconductor...
US-7,994,022 Semiconductor substrate and semiconductor device and manufacturing method of the same
A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer...
US-7,994,021 Method of manufacturing semiconductor device
A method of forming a semiconductor device is provided, including a step of forming a layer which absorbs light over one face of a first substrate, a step of...
US-7,994,020 Method of forming finned semiconductor devices with trench isolation
A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate...
US-7,994,019 Silicon-ozone CVD with reduced pattern loading using incubation period deposition
Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are...
US-7,994,018 Method for fabricating semiconductor device
A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a...
US-7,994,017 Method of manufacturing silicon carbide self-aligned epitaxial MOSFET for high powered device applications
A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a...
US-7,994,016 Method for obtaining quality ultra-shallow doped regions and device having same
A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a...
US-7,994,015 NMOS transistor devices and methods for fabricating same
NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a...
US-7,994,014 Semiconductor devices having faceted silicide contacts, and related fabrication methods
The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts...
US-7,994,013 Semiconductor device and method of fabricating the semiconductor device
A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions...
US-7,994,012 Semiconductor device and a method of manufacturing the same
To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that...
US-7,994,011 Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method
A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second...
US-7,994,010 Process for fabricating a semiconductor device having embedded epitaxial regions
A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a...
US-7,994,009 Low cost transistors using gate orientation and optimized implants
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by...
US-7,994,008 Transistor device with two planar gates and fabrication process
A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The...
US-7,994,007 Semiconductor device and method for manufacturing
A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first...
US-7,994,006 Manufacturing method of semiconductor device
A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a...
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